Multioperand Addition

1
Multi-operand Addition

• Consider the Following Addition SUM
  a0 for (i1 iltN i) SUM SUM
  ai

a7
a6
a5
a4
a3
a2
a1
a0
a7a6
a5a4
a3a2
a1a0
a7a6a5a4
a3a2a1a0
a7a6a5a4a3a2a1a0
2
Multi-operand Addition
a7
a6
a5
a4
a3
a2
a1
a0
a7a6
a5a4
a3a2
a1a0
a7a6a5a4
a3a2a1a0
a7a6a5a4a3a2a1a0

• O(lg2N) Lower Bound Theoretical Lower Limit
• This is Binary Reduction Operation
• Theoretical Time to Add Two Values
• O(n) Carry Ripple Operation
• O(lg2n) CLG/CLA tree/Prefix/Carry Skip/Carry
  Select
• O(1) Avizienis/Takagi Signed Digit Arithmetic

3
Multiplication

• Multiplication Requires Multi-operand Addition
• Dot Product Requires Multi-operand Addition
• Defer Carry Assimilation
• Represent Intermediate Sums Redundantly

4
Implementation Serially
5
Implementation with Pipelining
6
Parallel Implementation
7
Parallel Implementation bit level
8
Parallel Implementation bit level
9
Carry Save Adders

• FA Used in This Configuration is Also Known as a
  32 Compressor

10
Dot Notation
32 Compressor
22 Compressor
11
Example Tree
12
Example Tree (cont)
13
Tabular Form Representation
14
Adder Tree Bus Sizes
15
Serial Carry Save Adder
16
Serial Carry Save Adder