Farhan Mohamed Ali W21 Jigar Vora W22 Sonali Kapoor W23 Avni Jhunjhunwala W24

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Presentation 4 MAD MAC 525
Farhan Mohamed Ali (W2-1)Jigar Vora
(W2-2)Sonali Kapoor (W2-3) Avni Jhunjhunwala
(W2-4)
W2
Design Manager Zack Menegakis
15th February, 2006 Gate Level Design
Project Objective Design a crucial part of a GPU
called the Multiply Accumulate Unit (MAC) which
will revolutionize graphics.
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MAD MAC 525 Status

• Project chosen
• Specifications defined
• Architecture
• Design
• Behavioral Verilog
• Testbenches
• Verilog Gate Level Design
• Floor plan (revised Updated)
• Schematic (adder)
• To be done
• Layout
• Extraction, LVS, post-layout simulation

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Recap - MAD MAC 525

• Multiply Add (MAD) / Multiply Accumulate Unit
  (MAC)
• Executes function ABC on 16 bit floating point
  inputs
• Multiply and add in parallel to greatly speed up
  operation
• Rounding is only performed only once so greater
  accuracy than individual multiply and add
  functions.
• MAD MAC accelerates FP16 blending to enable true
  HDR graphics
• Bright things can be really bright
• Dark things can be really dark
• And the details can be seen in both

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Design Decisions

• Using n pass shifters instead of regular gates
  for the muxes
• Increases speed --- ?
• Reduces transistor count
• Reduces area
• Complexity of the project remains the same

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Block Diagram
Input
Input
Input
16
16
16
5
RegArray A
RegArray B
RegArray C
10
10
10
5
5
Multiplier
Exp Calc
Align
5
14
22
35
Control Logic Sign Dtrmin
Leading 0 Anticipator
Adder/Subtractor
36
4
Normalize
14
5
Round
10
5
1
Reg Y
Output
16
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• Updated Estimated Transistor Count
• n-pass gates
• Registers (I/O, pipelining, threading)
  1800 1800
• Carry-Save Multiplier 3500 3500
• Carry-Select Adder/Subtractor 3700 3700
• Alignment Shifter 530 1500
• Leading 0 Anticipator 350 350
• Normalize 900 3400
• Rounding 300 300
• Exponents 700 700
• Total 11780 15250

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• Estimated area (in um sq)
• n-pass
• Registers 9000
• Multiplier 25000
• Adder 26500
• Align 3800
• Leading zero counter 2500
• Normalize 6500
• Round 2000
• Exponent calc 5000
• Total 80300

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Main Floorplan
Multiplier
Reg A
Reg C
Exp Calc
Reg B
Align C
Pipeline Reg
Pipeline Reg
Adder
Ld Zero
Pipeline Reg
Round
Normalize
Reg Y
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• Multiplier

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Input From Reg A
10
Input from Reg B
And Array 726 transistors
10
Full Adder Array 2640 transistors
Input To Adder
22
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Schematics

• Multiplier 11 x 11 Carry-Save Multiplier

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Schematics

• Leading Zero Counter Carry-Save Adder to count
  the leading zeroes of C

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Schematics

• Align Exponents N-pass shifter

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Schematics

• I bit N-pass shifter used in the align block

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Schematics

• Normalize n-Pass Shifter to shift the result of
  the adder by the amount given by the Leading Zero
  Counter

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• Shifter for the Normalize

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Schematics

• Round Incrementer and Shifter

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Critical Path
Input
Input
Input
16
16
16
5
RegArray A
RegArray B
RegArray C
10
10
10
5
5
Multiplier
Exp Calc
Align
5
22
14
35
Pipeline Reg
Pipeline Reg
Control Logic Sign Dtrmin
Leading 0 Anticipator
Adder/Subtractor
Pipeline Reg
36
4
Normalize
14
5
Round
10
5
1
Reg Y
16
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• Questions?