Title: DATA MANIPULATION
1DATA MANIPULATION
- Tian-Li Yu
- tianliyu_at_cc.ee.ntu.edu.tw
- Department of Electrical Engineering
- National Taiwan University
2Motherboard
CPU Slot
Memory Slot
From http//www.asus.com.tw
3Computer architecture
- CPU (central processing unit)
- Registers
- Memory
- Bus
- Motherboard
Textbook, Figure 2.1
4Adding values stored in memory
Textbook, Figure 2.2
5Machine instructions
- Data transfer
- LOAD, STORE, I/O
- Arithmetic/logic
- AND, OR, ADD, SUB, etc.
- SHIFT, ROTATE
- Control
- JUMP, HALT
- RISC (PPC, SPARC) vs. CISC (x86, x86-64)
6Architecture of a simple machine
Textbook, Figure 2.4
7Example of a machine instruction
Textbook, Figure 2.5
Store (3) the content of register no. 5 to the
memory cell addressed A7
Memory reference 28256 cells (bytes)
8Adding two values revisited
Possible assembly
Possible C
LOAD 5, 6C LOAD 6, 6D ADD 0, 5, 6 STORE 0,
6E HALT
c a b
Textbook, Figure 2.7
9Program execution
- Instruction register, program counter
- Machine cycle
Textbook, Figure 2.8
10Fetch
Textbook, Figure 2.7
11Logic/bit operations
AND 01010101 00001111 00000101 Setting the
first 4 bits to 0.
OR 01010101 00001111 01011111 Setting the
latter 4 bits to 1.
XOR 01010101 00001111 01011010 Inverting the
latter 4 bits.
12Shift/Rotation
- Logic shift
- 10100000 ? 01010000 (right)
- ? 01000000 (left)
- Arithmetic shift
- 10100000 ? 11010000 (right)
- ? 11000000 (left)
- Rotation
- 10100000 ? 01010000 (right)
- ? 01000001 (left)
13Controller
- Specialized
- General USB, FireWire
Textbook, Figure 2.13
14Memory-mapped I/O
Textbook, Figure 2.14
15Communication with other devices
- DMA direct memory access
- Once authorized, controllers can access data
directly from memory without notifying CPU. - Hand shaking
- 2-way communication
- Coordinating activities
- Parallel/Serial
- Transfer rate bit per second (bps, Kbps, Mbps,
etc)
16Pipelining
- Throughput increased
- Total amount of work accomplished in a given
amount of time. - Example pre-fetching
- Issue conditional jump
Time
Fetch
Decode
Execute
Fetch
Decode
Execute
Fetch
Decode
Execute
17Parallel/distributed computing
- Parallel
- Multiprocessor
- MIMD, SISD, SIMD
- Distributed
- Linking several computers via network
- Separate processors, separate memory
- Issues
- Data dependency
- Load balancing
- Synchronization
- Reliability
18To parallel xor not to parallel
- declare A0A99
- input A0, A1, A2
- for (i 3 i
- Ai Ai-2 Ai-3
declare A0A99 input A0 for (i 1 ii) Ai Ai-1 2
How to parallel?
for (i 3 iAi-3 Ai1 Ai-1 Ai-2 A99
A97 A96
CPU 0
2 CPUs
CPU 1
19Speedup Scaling
Gain
Number of processors
20Exercises
- Ch 2 5, 7, 15, 23, 28, 33, 39, 44, 48