Compact Architecture for HighThroughput Regular Expression Matching on FPGA

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Compact Architecture for High-Throughput Regular
Expression Matching on FPGA
Authors Yi-Hua E. Yang, Weirong Jiang and Viktor
K. Prasanna Publisher ACM/IEEE Symposium on
Architectures for Networking and Communication
Systems (ANCS' 08) Present Chen-Rong
Chang Date March, 18, 2009
Department of Computer Science and Information
Engineering National Cheng Kung University,
Taiwan R.O.C.
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Outline

• Basic Architecture on FPGA
• From Regular Expression to NFA
• From RE-NFA to HDL
• Architectural Optimizations
• Multi-Character Input Matching
• Centralized Character Classification
• Staging and Pipelining
• Performance Comparison

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From Regular Expression to NFA(1/4)
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From Regular Expression to NFA(2/4)
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From Regular Expression to NFA(3/4)
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From Regular Expression to NFA(4/4)
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From RE-NFA to HDL
EX Inputbcbc
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Architectural Optimizations

• We apply three optimizations to improve our basic
  design
• (1) multi-character input matching
• (2) centralized character classication
• (3) staging and pipelining
• While these concepts have been proposed in
  previous research the techniques used here are
  unique to our design and take advantage of the
  modularity of the proposed architecture.

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Multi-Character Input Matching
EX Input1bcbc Input2bca

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Centralized Character Classification
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Staging and Pipelining
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Performance Comparison(1/4)
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Performance Comparison(2/4)
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Performance Comparison(3/4)
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Performance Comparison(4/4)