Built-in Built-in-Testing for Base band and RF Integrated Circuits

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Built-in Built-in-Testing for Base band and RF
Integrated Circuits
Analog and Mixed-Signal Center
Edgar Sánchez-Sinencio
Texas AM University http//amsc.tamu.edu/
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Outline

• Analog/RF Testing Research Overview
• Switched Capacitor Spectrum Analyzer
• Fully Integrated Transfer-Function
  Characterization System
• CMOS RMS Detector for HF/RF Testing
• Summary of Publications

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Analog/RF Testing Research Overview

• Switched Capacitor Spectrum Analyzer ( low
  frequency)
• Robust SC techniques applied for magnitude
  response and harmonic distortion
  characterization.
• Applicable for high frequency testing through
  up/down conversion.
• Fully Integrated Transfer-Function
  Characterization System ( 100s MHz)
• Magnitude and phase response characterization at
  various nodes.
• Fully digital system control and output.
• Suitable for testing in the range of hundreds of
  MHz.
• CMOS RF RMS Detector (GHz)
• Characterization of RF transceiver building
  blocks at 2.4GHz.
• Testing of a 350 MHz Low Pass Boost Filter for
  read channels.

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Testing Strategy Conceptual Description
C H I P
External Digital Test System
Digital Interface
Analog Device Under Test
Information Processing
(DUT)
Test activation and control
-Frequency response (Magnitude and
Phase) -Harmonic Distortion
Test Circuitry
Characterization data
Test circuitry area ltlt DUT area
Pass/Fail
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Outline

• Analog/RF Testing Research Overview
• Switched Capacitor Spectrum Analyzer
• Fully Integrated Transfer-Function
  Characterization System
• CMOS RMS Detector for HF/RF Testing
• Summary of Publications

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Switched Capacitor Spectrum Analyzer
Clocks
Clocks

• A simple sinewave generator synchronized with
  a high-Q
• SC bandpass filter enables a precise magnitude
  response and harmonic distortion characterization
  of the DUT.

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On-Chip Spectrum Analyzer Operation
f0 is synchronized with fBP
fBP is digitally controlled
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Switched Capacitor Sinewave Generator
The Sinewave Generator is an integrator that
generates 16 steps per period of a Sinusoidal
wave.
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Chip MicrographAMI 0.5um CMOS technology
Sinewave Generator 280µm330µm Bandpass
Filter 400µm?330µm VGA 200µm?210µm ADC
420µm?330µm Total Area for BIT Circuitry
0.5mm2
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Chip Layout and Microphotograph

• AMI 0.5 µm process
• Total area 750µm ?550 µm

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Experimental Results Sinewave Generator
Time Domain
Spectrum

• Output frequency 10KHz
• Harmonic distortion for a 1Vpp output -38dBm
• Noise density lt -85 dBc
• Power consumption 50uW

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Experimental Results BP Filter and VGA
BP Filter Transfer Function
VGA output for different gains

• Q programmability (BP Filter) 30, 60 and 120
• Gain programmability (VGA) 0, 8, 12, 16 and 20dB
  
• Error in center frequency lt 0.4

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Testing a 2nd Order LP Filter Commercial
Spectrum Analyzer Vs. Proposed System
Test Setup
Test Setup
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Experimental Results Frequency Response
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Experimental Results Harmonic Distortion
3rd harmonic distortion at the input of the BP
filter -30dB Measured distortion with the
proposed system -29.3dB
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SC Spectrum Analyzer Summary

• The use of robust SC techniques yields accurate
  magnitude response and harmonic distortion
  on-chip measurements.
• Despite the frequency limitations of SC circuits,
  combining proposed techniques with of building
  blocks available in HF systems enables the
  application for testing of HF DUTs.
• Area overhead is 4, 10, and 3 for Audio
  processor, Line Driver for ADSL and Cellular
  transceiver, respectively.
• Experimental Results from a prototype in CMOS
  0.5um
• M. Mendez-Rivera, A. Valdes-Garcia, J.
  Silva-Martinez and E. Sánchez-Sinencio, An
  On-Chip Spectrum Analyzer for Analog Built-In
  Testing, in Journal of Electronic Testing
  Theory and Applications, vol. 21, pp. 205-219,
  June 2005.

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Fully Integrated Transfer-Function
Characterization System

• Magnitude and frequency response characterization
  at different nodes of the CUT.
• System includes frequency synthesizer, magnitude
  and phase detector and ADC.
• The control interface and the output are fully
  digital.
• The testing technique is robust to process
  variations.
• The system can be employed as a tester chip or
  for built-in characterization.
• Suitable for testing analog blocks and subsystems
  in the range of hundreds of MHz.
• Silicon area is 0.3mm2 in 0.35um CMOS technology.

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Outline

• Analog/RF Testing Research Overview
• Switched Capacitor Spectrum Analyzer
• Fully Integrated Transfer-Function
  Characterization System
• CMOS RMS Detector for RF Testing
• Summary of Publications

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Transfer Function Characterization
The transfer function of a circuit under test
(CUT) is obtained by comparing the amplitude and
phase of the signals at the input and output.
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Magnitude and Phase Detector
An analog multiplier sequentially performs 3
multiplication operations between the input and
output of the CUT. 3 DC voltages are generated
(X, Y, Z).
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How to determine the magnitude (B/A) and phase
(q) responses?

• Simple operations performed by the external
  digital tester

From









W
e

c
an obtain

• The measurements do not depend neither on
• The amplitude of the signal generator (A)
• Nor on the gain of the multiplier (K).

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Block Diagram of Chip Prototype with Integrated
CUT

• Full On-Chip Characterization System
• Transfer function can be characterized at
  multiple nodes
• A digital word selects the test frequency and the
  node

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Phase Amplitude DetectorAnalog multiplier
with LPF

• Transistors operating in the linear region (M1)
• Source follower (M2)

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Experimental Results Amplitude Phase Detector

• Dynamic range for amplitude detection is gt 30dB
• Phase detection error is lt 1 over 95 of the
  overall 360 range

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Simple and Robust VCO of the PLL

• Multivibrator Lowpass Filter
• VC controls both the frequency and LPF
• A relatively constant amplitude and distortion
  over 2-150MHz

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Signal Generator Experimental Results
Tuning Range
Output Spectrum Locked PLL
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7-bits Successive Approximation ADC

• Output is taken serially through Dout (MSB down
  to LSB).
• Can be employed to digitize (monitor) any DC
  voltage in the chip using less than 0.1mm2 of
  area.
• Experimental Results
• Power consumption less than 200 mwatt
• Conversion time 1.2ms

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ADC Experimental Results
End of Conversion Clock Data
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Chip MicrographTSCMC 0.35um CMOS technology
Amplitude Phase Detector (APD)
310µm180µm Frequency Synthesizer 380µm?390µm A
DC 300µm?300µm Total Area for BIT Circuitry
0.3mm2 Area for each CUT 0.5mm2
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Application as a Tester Chip Testing a 70MHz
PGA for ADSL
Experimental Results Gain Programmability
Test Setup
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Application Testing a 70MHz PGA for ADSL
Magnitude Response
Phase Response
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Complete System Testing On-Chip BPF
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Built-in Testing of Continuous Time Boost Filter

• RMS Detector at the filter Output
• Gives maximum Fault Coverage
• Functional testing of w3dB, Boost, DC Gain
• RMS Detector at the input Calibration path
• RMS Detector at An Intermediate Node
• Should maximize the incremental fault coverage.
• Should be able to allow additional loading due to
  power detector.

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Outline

• Analog/RF Testing Research Overview
• Switched Capacitor Spectrum Analyzer
• Fully Integrated Transfer-Function
  Characterization System
• CMOS RMS Detector for RF Testing
• Summary of Publications

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On-Chip RF RMS Detection Motivation

• Increasing need for SOC test cost reduction.
• Fast fault diagnosis is required to accelerate
  the product development phase and time-to-market.
• Observation of RF signal paths through DC
  voltages is an effective and low cost test method
  for RF systems.
• Some implementations exist in SiGe but full CMOS
  solutions are desirable.

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• RMS detection at different nodes of a wireless
  transceiver improves the fault diagnosis
  capabilities

Detection points
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LNA Test Example

• Setup LNA with RMS Det. at input and output
• LNA1 On Spec.
• LNA2 Faulty

Robust Method Gain and 1dB comp. can be measured
regardless of the rms dectors gain or linearity.
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RF RMS Detector Concept

• Desired Features
• High input impedance and low substrate noise
  injection.
• Low area overhead (lt10 of the entire transceiver
  area).
• Dynamic range suitable for the characterization
  of the CUT.

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Proposed RF RMS Detector
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Pre-rectification Current Amplification

• M1 - Common Source RF Input transistor - converts
  the ac input voltage to ac current.
• Two current mirrors (M2-M3 and M6-M9) magnify the
  AC current.
• R1 and R3 increase the bandwidth of the AC
  current mirrors.

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Current Rectification Positive Cycle

• The working principle is to turn M10 and M11 on
  and off using AC current.
• M10 and M11 are DC-biased in the weak inversion
  region.
• M10-M11 operate as a current mirror and the AC
  current is mirrored to the Low Pass Filter.

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Current Rectification Negative Cycle

• The AC current from C1, is extracted out of Cpar
  and IB_small.
• M10 and M11 go into cutoff (off-state) and no ac
  current is fed to the low pass filter.
• AC current is fed to the filter only during the
  positive cycle and hence the half-wave-rectificati
  on is performed.

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AC-DC Conversion Filtering

• Post-rectification consists of a Second-order
  Low-Pass Filter with I-V Conversion
• First pole is implemented in the PMOS Current
  Mirror Load formed by M12 and C2.
• R6 and C3 perform the Second Low-Pass Pole.

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Post Layout Simulation Results
Transfer Characteristic at 2.4 GHz
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RMS Detector Performance Summary
Area Overhead Analysis
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Integrated Prototype

• Implementation in TSMC 0.35mm process including
• Stand alone RMS Detector
• 2.4GHz LNA and Buffer with RMS detectors.

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Experimental Results
Wideband operation (1.5GHz), Dynamic Rangegt30dB
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Additional Application Built-in Testing of HF
Continuous Time Systems
Fault Diagnosis
CORE
HF RMS Detect
Boost Filter
On-Chip Signal Gen
Functional Testing
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RMS Detector at An Intermediate Node

• Capturing Q obviates the need of a dedicated
  phase detection
• Band-Pass node is more sensitive to captures Q
  errors than a Low-Pass Node.
• Biquad1 has an available BP node Biquad2 has a
  BP node cascaded with a second order LP

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Built-in Testing of Continuous Time Boost Filter
LP-1
LP-2
BQ1
BQ2
LPF3
BP-1
BP-2
RMS Detect 4
RMS Detect 2
RMS Detect 1
RMS Detect 2
Functional tests Fault Diagnosis for overall
Filter w3dB and DC gain, Boost Observable
BP Nodes Q Observable
Calibration Path
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Filter Characterization for Fault Diagnosis

• DC Gain and w3dB Observable at the output
• Boost Gain for different settings Observable at
  the output
• Q for the Filter Observable at the BP node of
  Biquad 1 and Biquad 2
• Boost Slope and the Stop-Band Slope Observable
  at the output

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Summary

• A practical CMOS RF RMS detector is developed for
  on-chip characterization of RF circuits and
  systems.
• A methodology for the use of this device in the
  gain and 1dB comp. measurement of an RF circuit
  is developed.
• An implementation in a standard 0.35mm CMOS
  process uses lt0.15mm2 of area and presents an
  input capacitance lt25fF. Experimental results
  show broadband operation from 900MHz to 2.4GHz.
• The direct on-chip measurement of signal
  amplitudes at RF frequencies is feasible in CMOS
  with a very low area and parasitic loading.

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Modified Architecture for Testing a HF DUT
Frequency response and linearity
characterizations can be performed
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Integral On-Chip Test of a Transceiver
Work in progress Combining RF RMS detection,
Transfer Function Characterization and a
Loop-back architecture.
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Outline

• Analog/RF Testing Research Overview
• Switched Capacitor Spectrum Analyzer
• Fully Integrated Transfer-Function
  Characterization System
• CMOS RMS Detector for RF Testing
• Summary of publications

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Recent Publications on Analog Testing

• A. Valdes-Garcia J. Silva-Martinez and E.
  Sanchez-Sinencio, An On-Chip Transfer Function
  Characterization System for Analog Built-In
  Testing, IEEE VLSI Test Symposium, pp. 261-266,
  April 2004.
• A. Valero-Lopez, A. Valdes-Garcia and E.
  Sanchez-Sinencio, Frequency Synthesizer for
  On-Chip Testing and Automated Tuning, IEEE
  International Symposium on Circuits and Systems,
  pp. 561-568, May 2004.
• M. Mendez-Rivera, A. Valdes-Garcia, J.
  Silva-Martinez and E. Sanchez-Sinencio, An
  On-Chip Spectrum Analyzer for Analog Built-In
  Testing, Journal of Electronic Testing Theory
  and Applications, vol. 21, pp.205-219, June 2005.
  Most downloaded paper from the website of this
  journal (06/05- present).
• A. Valdes-Garcia, R. Venkatasubramanian, R.
  Srinivasan, J. Silva-Martinez and E.
  Sanchez-Sinencio, A CMOS RF RMS Detector for
  Built-in Testing of Wireless Receivers, IEEE
  VLSI Test Symposium, pp. 249-254, May 2005.
• A. Valdes-Garcia J. Silva-Martinez and E.
  Sanchez-Sinencio, On-Chip Testing Techniques for
  RF Wireless Transceivers, Invited to IEEE Design
  Test Journal.
• A. Valdes-Garcia J. Silva-Martinez and E.
  Sanchez-Sinencio, On-Chip Testing Techniques for
  Analog and RF Integrated Circuits, To be
  presented at Semiconductor Research Corporation
  (SRC) TECHCON Conference, October 2005.

Alberto Valdes-Garcia 1st place winner IEEE Test
Technology Technical Council (TTTC) Doctoral
Thesis Award