CS152: Computer Architecture and Engineering Lecture 9 Designing Single Cycle Control Randy H' Katz,

1
CS152 Computer Architectureand
EngineeringLecture 9Designing Single Cycle
ControlRandy H. Katz, InstructorSatrajit
Chatterjee, Teaching AssistantGeorge Porter,
Teaching Assistant
2
Recap Summary from last time

• 5 steps to design a processor
• 1. Analyze instruction set gt datapath
  requirements
• 2. Select set of datapath components establish
  clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that effects
  the register transfer.
• 5. Assemble the control logic
• MIPS makes it easier
• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates
• Single cycle datapath ? CPI1, Cycle Time long!

3
Recap The MIPS Instruction Formats

• All MIPS instructions are 32 bits long. The 3
  instruction formats
• R-type
• I-type
• J-type
• The different fields are
• op operation of the instruction
• rs, rt, rd the source and destination registers
  specifier
• shamt shift amount
• funct selects the variant of the operation in
  the op field
• address / immediate address offset or immediate
  value
• target address target address of the jump
  instruction

4
An Abstract View of the Implementation
Control
Ideal Instruction Memory
Control Signals
Conditions
Instruction
Rd
Rs
Rt
5
5
5
Instruction Address
A
Data Address
Data Out
32
Rw
Ra
Rb
32
Ideal Data Memory
32
32 32-bit Registers
Next Address
Data In
B
Clk
Clk
32
Datapath
5
Recap A Single Cycle Datapath

• Rs, Rt, Rd and Imed16 hardwired into datapath
  from Fetch Unit
• We have everything except control signals
  (underline)
• Todays lecture will show you how to generate the
  control signals

Instructionlt310gt
nPC_sel
Instruction Fetch Unit
lt1115gt
lt015gt
Rt
Rd
lt2125gt
lt1620gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr
ALUctr
5
5
5
Zero
MemtoReg
MemWr
busA
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
6
Recap Meaning of the Control Signals

• nPC_MUX_sel 0 ? PC lt PC 4 1 ? PC lt PC
  4 SignExt(Im16) 00
• Later in lecture higher-level connection between
  mux and branch cond

7
Recap Meaning of the Control Signals

• MemWr 1 ? write memory
• MemtoReg 0 ? ALU 1 ? Mem
• RegDst 0 ? rt 1 ? rd
• RegWr 1 ? write register

• ExtOp zero, sign
• ALUsrc 0 ? regB 1 ? immed
• ALUctr add, sub, or

RegDst
ALUctr
MemtoReg
MemWr
Equal
Rt
Rd
0
1
Rs
Rt
RegWr
5
5
5
busA

Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
0
32
busB
32
0
32
Mux
Mux
Clk
32
WrEn
Adr
1
1
Data In
Data Memory
Extender
imm16
32
16
Clk
ExtOp
ALUSrc
8
RTL The Add Instruction

• add rd, rs, rt
• memPC Fetch the instruction from
  memory
• Rrd lt- Rrs Rrt The actual operation
• PC lt- PC 4 Calculate the next
  instructions address

9
Instruction Fetch Unit at the Beginning of Add

• Fetch the instruction from Instruction memory
  Instruction lt- memPC
• This is the same for all instructions

Instructionlt310gt
nPC_MUX_sel
4
00
PC
Clk
imm16
PC Ext
10
The Single Cycle Datapath During Add

• Rrd lt- Rrs Rrt

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
lt1115gt
lt015gt
Rt
Rd
lt2125gt
lt1620gt
Clk
RegDst 1
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 1
5
5
5
MemtoReg 0
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 0
ExtOp x
11
Instruction Fetch Unit at the End of Add

• PC lt- PC 4
• This is the same for all instructions except
  Branch and Jump

Instructionlt310gt
nPC_MUX_sel
4
0
00
PC
1
Clk
imm16
12
The Single Cycle Datapath During Or Immediate

• Rrt lt- Rrs or ZeroExtImm16

Instructionlt310gt
nPC_sel
Instruction Fetch Unit
lt1115gt
lt015gt
Rt
Rd
lt2125gt
lt1620gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
Zero
MemWr
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
13
The Single Cycle Datapath During Or Immediate

• Rrt lt- Rrs or ZeroExtImm16

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
lt1115gt
lt015gt
Rt
Rd
lt2125gt
lt1620gt
Clk
RegDst 0
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr Or
RegWr 1
5
5
5
MemtoReg 0
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 0
14
The Single Cycle Datapath During Load

• Rrt lt- Data Memory Rrs SignExtimm16

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
lt1115gt
lt015gt
Rt
Rd
lt2125gt
lt1620gt
Clk
RegDst 0
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 1
5
5
5
MemtoReg 1
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
1
WrEn
Adr
1
Data In
32
Data Memory
32
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
15
The Single Cycle Datapath During Store

• Data Memory Rrs SignExtimm16 lt- Rrt

Instructionlt310gt
nPC_sel
Instruction Fetch Unit
Rt
Rd
lt015gt
lt2125gt
lt1620gt
lt1115gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
Zero
MemWr
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
16
The Single Cycle Datapath During Store

• Data Memory Rrs SignExtimm16 lt- Rrt

Instructionlt310gt
nPC_sel 4
Instruction Fetch Unit
lt1115gt
lt015gt
Rt
Rd
lt2125gt
lt1620gt
Clk
RegDst x
0
1
Mux
ALUctr Add
Imm16
Rd
Rs
Rt
Rs
Rt
RegWr 0
5
5
5
MemtoReg x
busA
Zero
MemWr 1
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
32
Data In
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 1
ExtOp 1
17
The Single Cycle Datapath During Branch

• if (Rrs - Rrt 0) then Zero lt- 1
  else Zero lt- 0

Instructionlt310gt
nPC_sel Br
Instruction Fetch Unit
lt1115gt
lt015gt
Rt
Rd
lt2125gt
lt1620gt
Clk
RegDst x
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr Sub
RegWr 0
5
5
5
MemtoReg x
busA
Zero
MemWr 0
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
32
busB
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc 0
ExtOp x
18
Instruction Fetch Unit at the End of Branch

• if (Zero 1) then PC PC 4
  SignExtimm164 else PC PC 4

Instructionlt310gt
nPC_sel
Zero

• What is encoding of nPC_sel?
• Direct MUX select?
• Branch / not branch
• Lets choose second option

nPC_MUX_sel
4
00
0
PC
1
Clk
imm16
19
Step 4 Given Datapath RTL -gt Control
Instructionlt310gt
Inst Memory
lt1115gt
lt2125gt
lt015gt
lt2125gt
lt1620gt
Adr
Op
Fun
Imm16
Rd
Rs
Rt
Control
ALUctr
RegDst
ALUSrc
ExtOp
MemtoReg
MemWr
nPC_sel
RegWr
Zero
DATA PATH
20
Summary of Control Signals
inst Register Transfer ADD Rrd lt Rrs
Rrt PC lt PC 4 ALUsrc RegB, ALUctr
add, RegDst rd, RegWr, nPC_sel
4 SUB Rrd lt Rrs Rrt PC lt PC
4 ALUsrc RegB, ALUctr sub, RegDst rd,
RegWr, nPC_sel 4 ORi Rrt lt Rrs
zero_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Z, ALUctr or, RegDst rt, RegWr,
nPC_sel 4 LOAD Rrt lt MEM Rrs
sign_ext(Imm16) PC lt PC 4 ALUsrc Im,
Extop Sn, ALUctr add, MemtoReg,
RegDst rt, RegWr, nPC_sel 4 STORE MEM
Rrs sign_ext(Imm16) lt Rrs PC lt PC 4
ALUsrc Im, Extop Sn, ALUctr add, MemWr,
nPC_sel 4 BEQ if ( Rrs Rrt ) then PC
lt PC sign_ext(Imm16) 00 else PC lt PC
4 nPC_sel Br, ALUctr sub
21
Summary of the Control Signals
func
10 0000
See
10 0010
We Dont Care -)
Appendix A
op
00 0000
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
22
Concept of Local Decoding
func
ALUctr
op
6
Main Control
3
ALUop
6
N
ALU
23
Encoding of ALUop

• In this exercise, ALUop has to be 2 bits wide to
  represent
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, and (4) Subtract
• To implement the full MIPS ISA, ALUop has to be 3
  bits to represent
• (1) R-type instructions
• I-type instructions that require the ALU to
  perform
• (2) Or, (3) Add, (4) Subtract, and (5) And
  (Example andi)

24
Decoding of the func Field
25
Truth Table for ALUctr
functlt30gt
Instruction Op.
0000
add
0010
subtract
0100
and
0101
or
1010
set-on-less-than
26
Logic Equation for ALUctrlt2gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt2gt
0
x
1
x
x
x
x
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1
This makes funclt3gt a dont care

• ALUctrlt2gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt2gt funclt1gt
  !funclt0gt

27
Logic Equation for ALUctrlt1gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt1gt
0
0
0
x
x
x
x
1
0
x
1
x
x
x
x
1
1
x
x
0
0
0
0
1
1
x
x
0
0
1
0
1
1
x
x
1
0
1
0
1

• ALUctrlt1gt !ALUoplt2gt !ALUoplt1gt
• ALUoplt2gt !funclt2gt !funclt0gt

28
Logic Equation for ALUctrlt0gt
ALUop
func
bitlt2gt
bitlt1gt
bitlt0gt
bitlt2gt
bitlt1gt
bitlt0gt
bitlt3gt
ALUctrlt0gt
0
1
x
x
x
x
x
1
1
x
x
0
1
0
1
1
1
x
x
1
0
1
0
1

• ALUctrlt0gt !ALUoplt2gt ALUoplt1gt
• ALUoplt2gt !funclt3gt funclt2gt
  !funclt1gt funclt0gt
• ALUoplt2gt funclt3gt !funclt2gt
  funclt1gt !funclt0gt

29
ALU Control Block

• ALUctrlt2gt !ALUoplt2gt ALUoplt0gt
• ALUoplt2gt !funclt2gt funclt1gt
  !funclt0gt
• ALUctrlt1gt !ALUoplt2gt !ALUoplt1gt
• ALUoplt2gt !funclt2gt !funclt0gt
• ALUctrlt0gt !ALUoplt2gt ALUoplt1gt ALUoplt2gt
  !funclt3gt
  funclt2gt !funclt1gt funclt0gt ALUoplt2gt
  funclt3gt !funclt2gt funclt1gt
  !funclt0gt

30
Step 5 Logic For Each Control Signal

• nPC_sel lt if (OP BEQ) then Br else 4
• ALUsrc lt if (OP Rtype) then regB else
  immed
• ALUctr lt if (OP Rtype) then
  funct elseif (OP ORi) then OR elseif
  (OP BEQ) then sub else add
• ExtOp lt _____________
• MemWr lt _____________
• MemtoReg lt _____________
• RegWr lt_____________
• RegDst lt _____________

31
Step 5 Logic for Each Control Signal

• nPC_sel lt if (OP BEQ) then Br else 4
• ALUsrc lt if (OP Rtype) then regB else
  immed
• ALUctr lt if (OP Rtype) then
  funct elseif (OP ORi) then OR
  elseif (OP BEQ) then sub else
  add
• ExtOp lt if (OP ORi) then zero else sign
• MemWr lt (OP Store)
• MemtoReg lt (OP Load)
• RegWr lt if ((OP Store) (OP BEQ)) then
  0 else 1
• RegDst lt if ((OP Load) (OP ORi)) then
  0 else 1

32
Truth Table for the Main Control
op
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
ori
lw
sw
beq
jump
RegDst
1
0
0
x
x
x
ALUSrc
0
1
1
1
0
x
MemtoReg
0
0
1
x
x
x
RegWrite
1
1
1
0
0
0
MemWrite
0
0
0
1
0
0
nPC_sel
0
0
0
0
1
0
Jump
0
0
0
0
0
1
ExtOp
x
0
1
1
x
x
ALUop (Symbolic)
R-type
Or
Add
Add
xxx
Subtract
ALUop lt2gt
1
0
0
0
x
0
ALUop lt1gt
0
1
0
0
x
0
ALUop lt0gt
0
0
0
0
x
1
33
Truth Table for RegWrite
op
00 0000
00 1101
10 0011
10 1011
00 0100
00 0010
R-type
ori
lw
sw
beq
jump
RegWrite
1
1
1
0
0
0

• RegWrite R-type ori lw
• !oplt5gt !oplt4gt !oplt3gt !oplt2gt !oplt1gt
  !oplt0gt (R-type)
• !oplt5gt !oplt4gt oplt3gt oplt2gt !oplt1gt
  oplt0gt (ori)
• oplt5gt !oplt4gt !oplt3gt !oplt2gt oplt1gt
  oplt0gt (lw)

RegWrite
34
PLA Implementation of the Main Control
RegWrite
ALUSrc
RegDst
MemtoReg
MemWrite
Branch
Jump
ExtOp
ALUoplt2gt
ALUoplt1gt
ALUoplt0gt
35
A Real MIPS Datapath (CNS T0)
36
Putting it All Together A Single Cycle Processor
ALUop
ALU Control
ALUctr
3
func
RegDst
op
3
Main Control
Instrlt50gt
6
ALUSrc
6

Instrlt3126gt
Instructionlt310gt
nPC_sel
Instruction Fetch Unit
lt1115gt
lt015gt
Rt
Rd
lt2125gt
lt1620gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
MemWr
Zero
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Instrlt150gt
Clk
ALUSrc
ExtOp
37
Recap An Abstract View of the Critical Path
(Load)

• Register file and ideal memory
• The CLK input is a factor ONLY during write
  operation
• During read operation, behave as combinational
  logic
• Address valid gt Output valid after access time.

Critical Path (Load Operation) PCs
Clk-to-Q Instruction Memorys Access Time
Register Files Access Time ALU to
Perform a 32-bit Add Data Memory Access
Time Setup Time for Register File Write
Clock Skew
Ideal Instruction Memory
Instruction
Rd
Rs
Rt
Imm
5
5
5
16
Instruction Address
A
Data Address
32
Rw
Ra
Rb
32
Ideal Data Memory
32
32 32-bit Registers
Next Address
Data In
B
Clk
Clk
32
38
Worst Case Timing (Load)
Clk
Clk-to-Q
New Value
Old Value
PC
Instruction Memory Access Time
Rs, Rt, Rd, Op, Func
Old Value
New Value
Delay through Control Logic
ALUctr
Old Value
New Value
ExtOp
Old Value
New Value
ALUSrc
Old Value
New Value
MemtoReg
Old Value
New Value
Register Write Occurs
RegWr
Old Value
New Value
Register File Access Time
busA
Old Value
New Value
Delay through Extender Mux
busB
Old Value
New Value
ALU Delay
Address
Old Value
New Value
Data Memory Access Time
busW
Old Value
New
39
Drawback of this Single Cycle Processor

• Long cycle time
• Cycle time must be long enough for the load
  instruction
• PCs Clock -to-Q
• Instruction Memory Access Time
• Register File Access Time
• ALU Delay (address calculation)
• Data Memory Access Time
• Register File Setup Time
• Clock Skew
• Cycle time for load is much longer than needed
  for all other instructions

40
Preview

• Next Time MultiCycle Data Path
• CPI ? 1, CycleTime much shorter (1/5 of time)

41
Summary

• Single cycle datapath gt CPI1, CCT gt long
• 5 steps to design a processor
• 1. Analyze instruction set gt datapath
  requirements
• 2. Select set of datapath components establish
  clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
  determine setting of control points that effects
  the register transfer.
• 5. Assemble the control logic
• Control is the hard part
• MIPS makes control easier
• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates

Processor
Input
Control
Memory
Output
42
Where To Get More Information?

• Chapter 5.1 to 5.3 of your text book
• David Patterson and John Hennessy, Computer
  Organization Design The Hardware / Software
  Interface, Second Edition, Morgan Kaufman
  Publishers, San Mateo, California, 1998.
• One of the best PhD thesis on processor design
• Manolis Katevenis, Reduced Instruction Set
  Computer Architecture for VLSI, PhD
  Dissertation, EECS, U C Berkeley, 1982.
• For a reference on the MIPS architecture
• Gerry Kane, MIPS RISC Architecture, Prentice
  Hall.