ASTER Ingnierie

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ASTER Ingénierie
February 2002 - Mr Christophe LOTZ

• TESTWAY
• The reference in Testability Analysis

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Why testability?
Technical reasons

• To allow effective production tests to be
  completed according to
• The increased functional complexity of electronic
  products (devices, subassembly).
• The increased device density at PCB level
  (Surface Mounted Technology, Fine Pitch,PGA,
  BGA, buried via).

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Why testability?
Technical reasons

• To increase test efficiency
• Speed up test execution.
• Improve fault detection.
• Provide accurate diagnostics to aid fault
  analysis.
• Simplify repair cycle.
• Reuse prototype test (Boundary-Scan).

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Why testability?
Economical reasons

• To reduce
• ATE investments
• Test program set cost
• Test program development cost
• Fixture cost
• Test time
• Time to market

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Design For Test

• According to usual methodology, a test expert
  works with technical drawings to produce a
  testability analysis.
• Have all testability problems been identified?
• Multiple sheet designs can lead to 3 or 4 days
  work.
• Often, this task is completed too late.

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Design For Test
A new concept the TestWay software

• Quick testability analysis at schematic board
  level.
• Design and test people get automatically a
  readable testability report to work around.

The best way to check TEST requirements is early
within the board DESIGN cycle.
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Design For Test
TestWay can be directly exploited

• By the board schematic designer on its
  workstation because testability analysis is run
  early in the design phase.
• By the Company Testability Manager, cutting down
  on testability analysis task.
• By the Test Team, predicting potential problems,
  helping to choose the best test strategy,
  measuring the real test efficiency.

SUCCESS
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Structure

• Click on the message in the TestWay report and
  view the problem directly on schematic and/or
  layout.

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Synopsis
Schematic Layout importer
Model importer
Reporting
Modifier merger
Schematic Layout viewers
TestWay - Testability Frame
Design Rules Checker
DFT Rules Checker
Custom Rules Checker
Test Point Saver
Test Coverage Analyzer
Test Interfaces
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Applications

• TestWay handles a large spectrum of applications
  from design to test.
• For today, we will discuss the following points
• Cad importer and merger
• Rules checking.
• Test Point Saver.
• Test coverage analysis.
• Boundary-Scan test.
• Combination with ICT, MDA or FPT.

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CAD Importers

• TestWay supports 34 CAD importers for both
  schematic and layout information.
• Schematic model translators and BSDL compiler.

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Board modifier and merger

• TestWay can modify the original connectivity
• Simulate any design modifications
• add/remove pins or devices,
• interconnect nets, pins or devices,
• insert boundary-scan capabilities.
• Remove not mounted components.
• Add test logic or test cables.
• Interconnect boards together for a system
  analysis (mother board with daughter boards).

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Model concept

• TestWay requires a model for each device in case
  there are no testability information included in
  the schematic description.
• Keywords are used to describe device or pin
  properties. These keywords can be user-defined.
• For device, Classes describe electrical
  characteristics (analog, digital, mixed),
  functions (microprocessor, RAM, diode, ),
  testability features (Tristate, Boundary-scan,
  ).
• For pin, properties have the same functions.

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Model example

• OCTAL D-Type Flip-Flop with 3-state outputs

DEVICE 54374 CLASS BUFFER,
TRISTATE PINS 1, OE, IN, CMD 2, Q0, OUT, TR
I 3, D0, IN 4, D1, IN 5, Q1, OUT, TRI
6, Q2, OUT, TRI 7, D2, IN 8, D3, IN
9, Q3, OUT, TRI 10, GND, POWER_0 11, CP
, IN, CLK 12, Q4, OUT, TRI 13, D4, IN 1
4, D5, IN 15, Q5, OUT, TRI 16, Q6, OUT, TR
I 17, D6, IN 18, D7, IN 19, Q7, OUT,
TRI 20, VCC, POWER_1
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Design Rules

• Basis design rules checking (driver vs. receiver,
  net configuration)
• Electro Static Discharge protection
• Noise immunity
• Technological requirements (TTL/CMOS or voltage
  compatibility, security devices and protection,
  clock propagation)

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DFT Rules

• Testability rules from military standard or
  industry (functional test, in-circuit test,
  boundary-scan).
• Connectivity oriented rules (control
  accessibility, chain, loop, conflicts)
• Device oriented rules (Oscillator, counter,
  microprocessor, EEPROM, PLD, )
• For example,
• Disable checks
• Boundary-scan (IEEE 1149.1)

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Custom Rules

• Despite providing a lot of rules about design,
  testability and design-to-test, TestWay may not
  include your own rules.
• There is now not any problem to define such
  rules.
• Rather than a C-based language with a library of
  specific functions, instead of a global database
  with SQL queries, TestWay provides a solution to
  describe your rules using a natural language.

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Custom Rules

• Your own requirements in order to check
• Pin or device oriented rules
• Technological requirements
• In-Circuit programming for flash EEPROM or FPGA
• Specific rules for ASIC
• Any customers rules!
• You never have twice the same problem as TestWay
  capitalizes your knowledgetrough the customers
  rules.

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Custom Rules Example

• ! Defining design and technological rules
• Pin (INDIGITAL) is not floating.
• Pin of device (3V) is not connected to a device
  (5V).
• ! To check PLD FPGA test
• Pin ISPEN of device (ISPLSI) is connected to a
  pull-up.
• Pin PWRDWN? (IN) of device XC30?? is accessible.
• Pin M0 (IN) of device XC30?? is accessible.
• ! To check IN-CIRCUIT programming of EEPROM
• Pin A9 of device AM27C010 is protected by a
  device (DIODE).
• Pin CE_ of device AM27C010 is accessible.
• Pin PGM_ of device AM27C010 is accessible.

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Test Point Saver
From schematic

• TestWay optimizes the test point requirements
  against the test strategy.
• Reduce the number of required Test Points whilst
  still maintaining a high level of fault coverage.
• Practical answer in order to bypass lost of
  physical accesses.
• Perfect solution for prototype test retain the
  20 of nets which cover 80 of the board.
• Manage the combination of several test strategies
  in order to control the test partitioning.

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Test Point Saver
Electrical View
Physical view
TestWay
Select the absolutely required test access points
to guarantee a good fault coverage.
Test points required
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Test Point Saver
From layout

• TestWay organizes the test strategy against the
  test points available.
• Predict test coverages for several test
  approaches BST, FPT, ICT, MDA...
• Combine physical and electrical characteristics
  through customers rules to choose the more
  convenient combination.
• Evaluate different scenarios to choose the most
  efficient.

We produce a testability report where the other
product just generate an accessibility report!
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Test Point Saver
Electrical View
Physical view
TestWay
Test point locations
Check fault coverage according to the real
physical accesses.
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Test Coverage

• TestWay provides coverage metrics
• Predict test coverage from schematic or layout.
• Load test programs or test coverage reports from
  any test or inspection machine (AOI, AXI, BST,
  FPT, ICT, FCT).
• Provide a set of macros which compute the real
  coverage per device, net and pin.
• Custom rules check development rules and
  define the optimization criteria in order to
  manage properly the redundancy tests.
• Custom files produce various report formats.

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Test Coverage

• New test strategies combine several test systems.
• For one test system,
• Produces dedicated test coverage report.
• Checks real coverage against theoretical.
• Controls test program development rules.
• For a line with several test systems,
• Identifies uncovered area.
• Manages redundancy tests for possible
  optimization.

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Test Interfaces

• TestWay produces test program and models for
  several test systems
• All data can be produced from Schematic or Layout!

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Boundary-Scan

• To fully use Boundary-Scan capabilities,
  Schematic Testability Analysis is required to
  insure/improve the Boundary-Scan test coverage
• Check testability Rules.
• Evaluate Test Strategy.
• Predict Test Coverage.
• Optimize Test Points at Schematic level.
• Check Test Points availability at Layout level.
• Control real test coverage against theoretical
  coverage.

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Boundary-Scan

• Boundary-Scan is used by test people for
  production test
• Mixed In-Circuit Test / Boundary-Scan Test
  provides a high coverage on all parts. Lost of
  physical accesses is solved. Fixture and
  In-Circuit Test program can be optimized.
• Flying Probe Test Time may be cut up to 50
  combining Boundary-Scan coverage (even if the two
  test systems are not integrated!).

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Boundary-Scan vs. ICT
Electrical view
Physical view
Schematic
Layout
CIM
TestWay
Back-annotation Layout CIM
Test Strategy
Optimized fixture ICT program
Boundary-Scan Test Coverage report
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Boundary-Scan vs. FPT
Electrical view
Physical view
Schematic
Layout
CIM
TestWay
Test Strategy
FPT program
Optimist and pessimist optimizers Same Test
efficiency, different diagnosis capabilities.
Optimized FPT programs (up to 50 of test time
saved)
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Main customers

• TestWay main customers
• Alcatel, Alstom, CSEE Transport, Dassault
  Aviation, Dassault Automatisme, EADS, Lucent
  Technologies, Motorola, Nortel Networks, RATP,
  Schlumberger, Sagem, Siemens Telecom, Siemens
  Automotive, SCI, Solectron, Thales, Via Systems,
  3COM

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Contact

• ASTER Ingénierie
• 25 rue des Landelles
• 35510 Cesson-Sévigné, France
• Your local distributor contact on request!
• 33 (0)2 99 53 71 71
• Fax [phone]
• E-mail sales_at_aster-ingenierie.com