ChungPing Chen

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NTU 921 U9360Advanced VLSI Design-A Practical
Approach

• Chung-Ping Chen (???)

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Advanced VLSI Design

• Instructor
• Charlie Chung-Ping Chen, cchen_at_cc.ee.ntu.edu.tw
• TA
• TBD
• Text
• Principles of CMOS design A system
  perspective, Neil Weste and Kamran Eshraghian,
  Addison-wesley
• CAD Tools Cadence CIC flow. www.cic.org.tw
• http//cc.ee.ntu.edu.tw/chen

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Conferences Journals

• IEEE Transactions on VLSI Systems
• IEEE Transactions on CAD of ICs
• IEEE Journal of Solid State Circuits
• IEEE VLSI Circuits Symposium
• Journal of Electronic Testing
• ACM Design Automation Conference
• IEEE International Conference on CAD
• IEEE Solid State Circuits Conference
• International symposium on Low-Power Electronics
  Design
• IEEE Conference on Computer Deisng
• IEEE International Test Conference

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Advanced VLSI Design

• Assignments
• Approximated 4 assignments will be given. The
  assignments will be due at the beginning of the
  class the due date specified. No late assignments
  will be accepted expect under extreme
  non-academic circumstances
• Project
• A major VLSI design project performed by a
  student team is required. The project will
  involve chip design and simulation using Cadence
  tools. More details will be provided in about
  three weeks

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Advanced VLSI Design

• Exams There will be a midterm exam and a final
  exam.
• Grading Homework 10, Midterm 20, Project 40,
  Final 30
• Any form of cheating will be heavily penalized
  and reported to the Dean of students and may
  result in a failing grade and more.
• Instructor reserves the right to change project
  requirements.

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Course Content

• Advanced Circuit Design
• Fundamental of modern ASIC Design Flow
• High-speed/Low Power Circuit Design Style
• Signal Integrity/Power Integrity Aware VLSI
  Design
• Special circuits design Power Ground/Clock/Memory
  
• Timing Analysis
• Advanced Microprocessor Design Techniques
• High-speed/low-power Microprocessor design
  technology and implementation
• Branch Perdition
• Out-of-order execution
• Threading

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Course Outline

• MOS, CMOS Logic, Layout techniques
• Inverter and Power Consumption
• Designing combinational logic gates in CMOS
• Static CMOS design Complementary CMOS
• Dynamic CMOS logic
• Low Power Design
• Designing sequential circuits
• Memory design
• Arithmetic building blocks

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Course Outline

• Signal and Power Integrity Issues and solutions
• Timing analysis
• Advanced Computer Architecture
• Instruction Set Architecture
• High Performance Pipelines
• Precise Traps Branch Prediction
• Superscalar Processors
• Power Efficiency
• System Architecture Studies (Pentium, Alpha,)

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Work hard?

• Good job opportunities M.S. Salary gt 65k in
  Silicon Valley
• Good research opportunities VLSI is a very
  active research area, University job Research
  centers (IBM, Intel, Lucent), Ph.D. salary 95K
• Why do you need to do exceptional well in this
  course
• You can claim you are good in VLSI during
  interview
• You will have overall understanding and practical
  design experience in VLSI design
• You are in good position to get a recommendation
  letter from me
• You will learn more than whats in the textbook
• You can maintain your straight A family
  tradition
• ...

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How to succeed

• Work hard, study hard
• Team work
• Learning, discussion, join project
• Do it (not only read it)- run simulations
• Do some research
• Journals or conference
• Read magazines EETIMES, EDN, . www.eetimes.com
• Look at stock news

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Course projects

• There will be several potential topics to choose
  and will be announced soon
• You can also suggest a project you like
• Goal
• Complete a medium size VLSI design from
  architecture to layout
• Get a practical experience from high level
  specification to layout completion
• Combine knowledge and VLSI like small
  microprocessor embeded microprocessor,
  networking, multimedia, DSP, and Graphics
• Start early and work together (but dont copy
  each other)

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Project proposal

• Project proposal and approved by 15 Oct, 5 final
  grade
• Project presentation in the last week of class
• 12-15 minute presentation
• 15 of final grade
• Project report due by the last day of class
• 15 of final grade

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IntroductionA Historical Perspective and
Future Trends
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The First Computer
The Babbage
Difference Engine
(1834)
25,000 parts
cost
17,470
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Digital Electronic Computing

• Started with the introduction of vacuum tube
• ENIAC for computing artillery firing tables in
  1946
• Integration density
• 80 feet long, 8.5 feet high, and several feet
  wide
• 18,000 vacuum tubes
• Did not go far due to reliability issues and
  excessive power consumption

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ENIAC - The first electronic computer (1946)
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Semiconductor Pioneers-Bipolar

• Bipolar transistors Bardeen (1947), Schockley
  (1949), replace Vacuum tube because
• low power consumption
• More reliable
• Larger integrated capacity
• First Bipolar digital logic Harris (1956)
• First Bipolar digital logic (combination of
  transistors) Harris (1956)
• 1960 Commercial logic gates Fairchild Micrologic
  family (lots of Intel folks originally from here)
• IC Logic family
• Transistor-Transistor Logic (TTL) 1962 (higher
  integration)
• Emitter-Coupled Logic (ECL) 1971 better
  performance-(sub nanosecond)
• Integrated Injection Logic (I2L) 1972 (high
  density, low power bipolar)

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Semiconductor Pioneers- MOSFET

• Basic principle J. Lilienfeld (1925)
• Fail due to insufficient knowledge of the
  materials and gate stability problems
• PMOS and NMOS transistors on the same substrate
  Weimer (1962), Waniass (1965)-- better integrated
  capacity
• CMOS logic introduced at 1963
• did not take off for more than two decades due to
  manufacture issues
• MOSFET Take off at early 1970s
• PMOS-only logic popular first
• NMOS-only logic 1972 by Intel Corp. (higher
  speed)
• High density (4Kbit!) MOS memory in 1970
• CMOS popular in late 1970 (low power)
• BiCMOS Combination of CMOS and Bipolar (high
  performance)
• Gallium Arsenide (high performance)

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Factors for successfulness

• Lower power
• Higher integration (high density, small die area)
• Higher speed
• Reliability
• Easy to design
• Cheaper (manufacture)

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Moore's First Law
..Gordon Moore 1960
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Evolution in Complexity
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Evolution in Transistor Count
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"Extrapolated" Year 1999 wafer size
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(No Transcript)
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Moore's Second Law
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Size of Team Explodes
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(No Transcript)
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Evolution in Speed/Performance
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Intel 4004 Micro-Processor
Manual design
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Intel Pentium (II) microprocessor
With Design Automation
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Silicon in 2010
Die Area 2.5x2.5 cm Voltage 0.6
V Technology 0.07 ?m
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Design Abstraction Levels
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Deal with complexity

• More hands
• Abstraction and design reuse
• Use logic gates instead of simple transistors
• Build library which can be repeatedly reused
  (standard cell)
• Design Automation
• Mapping logic specification to library Logic
  Synthesis
• Automatic Layout Physical design

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Next Week

• Lecture Notes
• Old http//courses.engr.wisc.edu/ecow/get/ece/755
  /1chen/notes/
• New http//cc.ee.ntu.edu.tw/cchen
• HSPICE Tutorial
• http//courses.engr.wisc.edu/ecow/get/ece/755/1che
  n/tutorials/
• Cadence Tutorial
• http//www.ece.utexas.edu/rpriya/Cadence/cadence.
  html
• Resource
• http//wwwold.cic.org.tw/training/index.html