Soft Errors in CAM and Their Impact On TLB Reliability

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Soft Errors in CAM and Their Impact On TLB
Reliability

• Feihui Li
• Swapna Dontharaju

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Introduction

• TLB - a small cache, to speed up address
  translation in processors with virtual memory
• Soft errors can significantly affect memories
• Because of spatial density, amount of information
  stored
• We are studying their impact on CAMs
• On the other hand, TLB is a major power consumer
• STRONG ARM processor, 17 of total power
  consumption due to TLB though designed for low
  power, and TLB is very small
• We have compared Soft Error Susceptibility in CAM
  designs that reduce the power consumption

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Analyzing the Basic CAM cell

• Write a 1(0)
• Pass transistors T1, T2 opened via Word line
• Bit set to 1, Bit to its inverse
• T6(T5) conducting, T5(T6) not ? storage of 1
• Search (1)
• Match line precharged high
• Search bit on Bit (1), its inverse on Bit (0)
• If 1 at Q, T8 propagates 0 (from Bit) to gate
  of T9
• T9 stays nonconducting, Matchline not
  discharged
• Obvious Questions
• During a Write, What if there is a flip at T1
  or T2
• Flip at both circuit will search instead
  mismatch?
• During a Search, If T7 / T8 flip will the
  result be correct?
• If T9 flips, Match line discharges even if no
  search?
• Strikes at T3, T4, T5, T6 Flip in the value
  stored?

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In the TLB ..

• A flip at any of the transistors connected to the
  match line can cause the match line, (even if
  search successful) to discharge.
• So even if address translation was available in
  the TLB, the instruction could have missed the
  TLB! Performance, power penalty.

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Designs studied

• Basic CAM
• Necessary to put all bit lines to 0, to
  precharge Match line high switching in bit
  lines
• Modified CAM
• Control line used, to precharge match line
  without putting to zero the bit lines reduces
  switching activity of bit lines.
• Toggling Match Line CAM
• CAM alternates between active high and active
  low match line output for every access reduces
  switching activity in match lines.

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Charge Induction Scenarios for CMOS circuits

• Cases II I Voltage at p node go up
• Cases III IV Voltage at n node go down.
• II IV wont affect logic state of circuit,
  node is already at logic value toward which
  injected charge will drive it
• III I affect logic value of node, may cause
  incorrect operation of circuit, modeled below

Resistors ? conducting transistors, Rectangles
?drain Current sources show direction of current
flow
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Experimental Setup

• When a 1 is stored in the CAM cell, Cases III
  I modeled as,
• Positive pulse at Q to induce a bit flip
• Negative pulse at Q to induce a bit flip
• Similar analysis when CAM cell stores a 0
• Qcritical a measure of the current required
  to flip a memory cell
• Qcritical of the nodes in the cell found Q,
  Q, T9.
• Using Micro Magic and HSPICE, current spikes
  can only be injected at nodes, (transistors
  lumped by interconnect say Q, Q) rather than
  each individual transistors. Not possible to
  study some of the interesting flips mentioned
  above, in isolation.

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Results
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Results

• Qcritical is different for each node
• Qcritical depends highly on state of the cell
  precharge, read or write
• Match line transistor T9 in Basic CAM, more
  susceptible to bit flip than other nodes

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Analysis
A method to estimate Soft Error Rate (SER) using
Qcritical has been developed by Hazucha and
Svensson Nflux intensity of Neutron flux,
CS area of crossection of node, Qs charge
collection efficiency, Qcritical minimum charge
collected due to a particle strike that causes a
bit flip Id drain current induced by the ion,
Tf flipping time Qcritical has been used as an
index to the SER.
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Work in progress..

• We are working on the following -
• Impact of technology scaling on SER of Basic
  CAM and TLB structure (180nm down to 70 nm)
• For a given technology, see whether the Basic
  CAM or the 6T-SRAM is more susceptible to soft
  errors for a given row of the TLB, which of
  them contributes more to SER
• Model Power consumption of a 16 word CAM, each
  word having 16 bits, using each of the above CAM
  cells
• Study the Qcritical Vs Power consumption
  tradeoffs

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Thank You !!

• Questions

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References

• 1 Thirugnanam, G. Vijay Krishnan, N. Irwin,
  M.J.A novel low power CAM design, Proceedings
  of the 14th Annual IEEE International ASIC/SOC
  Conference, Sept. 2001, Page(s) 198 -202
• 2 T.Juan, T.Lang and J.Navarro, Reducing TLB
  Power Requirements, Proceedings of the 1997
  International symposium on Low power electronics
  and design, 1997, pp. 196-201
• 3 V. Degalahal, N. Vijay Krishnan, M.J Irwin,
  "Analyzing Soft Errors in Leakage Optimized SRAM
  Design", In the Proceedings of VLSI Design
  conference January 2003, New Delhi, India
• 4 H Cha, J H Patel A logic level model for
  alpha particle hits in CMOS circuits Proceedings
  of the International Conference on Computer
  Design, 1993.
• 5 P. Hazucha and C. Svensson, Impact of CMOS
  technology scaling on the atmospheric neutron
  soft error rate, IEEE Transactions on Nuclear
  Science, 2000
• 6 D.C. Burger and T.M. Austin. The SimpleScalar
  tool-set, Version 2.0. Technical Report 1342,
  Dept. of Computer Science, UW, June 1997
• 7 The SimpleScalar tool-set. http//www.simplesc
  alar.com/