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PCI

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PCI. Peripheral Component Interconnect Bus. picture courtesy of newegg.com. History ... Picture courtesy of newegg.com. PCI. PCI - Express ... – PowerPoint PPT presentation

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Title: PCI


1
PCI
  • Peripheral Component Interconnect Bus

picture courtesy of newegg.com
2
History
  • PCI was developed by Intel and introduced in 1993
  • ISA, the bus architecture used at the time had
    become a bottleneck within the computer
  • Intel formed a PCI special interest group,
    contributed technology, and encouraged an open
    industry specification to prevent the
    complication of competing buses

3
History
  • PCI provided a tenfold performance gain over ISA
  • Plug and Play (PnP) capabilities made it easier
    for users to add expansion cards to their
    computers
  • PCI is used today in almost every computer
    platform

4
Specs
  • Parallel Communication
  • First version ran at 33MHz with 32 bit bus
    (133MBps)
  • Current version runs at 66MHz with 64 bit bus
  • Bus Clock Signal 133 MHz
  • Theoretical Max Transfer Rate 1GB/s

5
PCI
  • An interconnection system between a
    microprocessor and attached devices in which
    expansion slots are closely spaced for high speed
    operations.
  • Transmits 32 bits at a time in a 124-pin
    connection and 64 bits in a 188-pin connection in
    an expanded implementation.
  • Uses all active paths to transmit both address
    and data signals, sending the address on one
    clock cycle and the data on the next (Burst Mode)

6
PCI
  • The PCI bus treats all transfers as a burst
    operation.
  • Each cycle begins with an address phase followed
    by one or more data phases.
  • Data phases may repeat indefinitely, but are
    limited by a timer that defines the maximum
    amount of time that the PCI device may control
    the bus.
  • This timer is set by the CPU as part of the
    configuration space. Each device has its own
    timer
  • The same lines are used for address and data. The
    command lines are also used for byte enable
    lines. This is done to reduce the overall number
    of pins on the PCI connector

7
PCI Bus Signals
  • Address/Data Bus 64bit Address 64bit Data,
    Time Multiplexed
  • System Bus 2bits Clock/Reset
  • Interface Control Bus 7bits Ready,
    Acknowledge, Stop.
  • Parity Bus 2 bits, 1 for the 32 LSBs and 1
    for the 32 MSB bits
  • Errors Bus 2 bits, 1 for Parity and 1 for
    System
  • Command/Byte Enable 8 bits (0-3 _at_ 32bit, and
    4-7_at_ 64bit Bus)
  • 64MHz Control 6 bits (2) Enable/Running,
    (2) Present, (2) Ack/Req
  • Cache 2 Bits
  • Interrupt bus 4 bits
  • JTAG Bus 5 bits
  • Power 5, 3.3, 12, -12v, GND

8
Longevity
  • PCI is processor independent, so it can function
    in various markets with little change
  • Not wired into a specific processor, so
    manufacturers could standardize their I/O across
    multiple product groups
  • Flexible in its ability to support multiple form
    factors

9
Longevity
  • There are a limited number of hardware interrupts
    (IRQs) and the PCI bus is designed to share them.
  • ISA cards require a fixed IRQ to be assigned to
    the device

10
PCI
  • PCI was used from 1993 2004 as the standard
    local bus system within a computer
  • PCI specification standardized how expansion
    cards such as network cards install themselves
    and exchange information with the CPU
  • CPU clock speed has increased from 66 MHz in 1993
    to over 3GHz
  • The operational frequency of PCI has only
    increased once from 33MHz to 66MHz

11
PCI - X
  • PCI Extended
  • Improves upon the speed of PCI from 133 Mbps
    to up to 1Gbps
  • Created for servers to increase performance of
    high bandwidth devices, such as Gigabit Ethernet
  • Designed jointly by IBM, HP, and Compaq

12
PCI - Express
  • 3GIO (Third Generation Input/Output)
  • An I/O interconnect bus standard that expands on
    and doubles the data transfer rates of original
    PCI.
  • A two-way, serial connection that carries data in
    packets along two pairs of point-to-point data
    lanes, compared to the single parallel data bus
    of traditional PCI that routes data at a set
    rate.
  • Initial bit rates reach 2.5Gb/s per lane
    direction with data transfer rates of
    approximately 256MB/s.
  • 32x PCI Express has transfer rates of 8GB/s per
    stream (16GB/s duplex)
  • It was developed so that high-speed interconnects
    such as Firewire, USB 2.0, and Gigabit Ethernet
    would have an I/O architecture suitable for their
    high transfer speeds.

13
Asus Striker Extreme 775 NVIDIA nForce 680i ATX
(The Ultimate Gaming Motherboard) 339.99
Picture courtesy of newegg.com
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