Shannons Bound: At What Costs Architectures and Implementations of High Throughput Iterative Decoder

1
Shannons Bound At What Costs? Architectures
and Implementations of High Throughput Iterative
Decoders

• Engling Yeo
• January 14, 2003
• Department of Electrical Engineering and Computer
  SciencesUniversity of California, Berkeley

2
Background Coding
SNR vs. BER for rate 1/2 codes
0
10
-1
10
Uncoded
-2
10
Iterative
BER
Code
-3
10
Conv. Code
ML decoding
Capacity
Bound
-4
10
4 dB
C. Berrou and A. Glavieux, "Near Optimum Error
Correcting Coding And Decoding Turbo-Codes,"
IEEE Trans. Comms., Vol.44, No.10, Oct 1996.
0
1
2
3
4
5
6
SNR

• Key Problem Implementation Complexity
• !! Block size of 107 bits.

3
Types Iterative Codes

• Turbo codes
• Parallel concatenation Berrrou93, AgilentTM,
  STTM
• Serial concatenation Souvignier99
• Turbo product codes
• Hamming Comtech AHATM
• BCH Pyndiah99
• Low density parity check codes Gallager63,
  FlarionTM, AgereTM
• Density evolution Richardson00
• Finite field constructions Lin00
• Rammanujan graphs Rosenthal00
• Tornado codes Luby99, Digital FountainTM
• Turbo-coded modulation, equalization,

4
Belief Propagation Analogy

• Each event occurs with some prior probability.
• Posterior probability based on inference from a
  number of related events.

5
Constrained Coding and Iterative Decoding

• Each set represents a group of constrained bits
• e.g. even parity, cyclic codewords
• Decoding based on inferences passed between
  adjacent neighbors

H
D
G
B
A
F
E
C
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Highly Parallelizable Architectures
...
PE
PE
PE
PE
PE
PE
VC,1
VC,2
VC,3
VC,4
VC,N
VC,N-1
Check-to-Variable
PE
Processing Element
CV
Variable-to-Check
PE
PE
...
VC
VC
Processing Element
PE
PE
PE
CV,1
CV,2
CV,M
...
PE
PE
PE
PE
PE
PE
VC,1
VC,2
VC,3
VC,4
VC,N
VC,N-1
A. Blanksby and C. J. Howland, A 220mW 1-Gbit/s
1024-Bit Rate-1/2 Low Density Parity Check Code
Decoder, Proc IEEE CICC, Las Vegas, NV, USA, pp.
293-6, May 2001.
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Implementation Complexities

• Concatenated turbo code
• UMTS-3GPP application 81920 nodes (trellis
  states), 163840 edges
• Low density parity check code
• Magnetic storage application 5120 nodes (bits
  and parity checksums), 18432 edges
• Routing complexity of a massively parallel
  algorithm
• Edge connectivity disorganized in general
• Quantization effects in fixed-point
  implementations with high fan-in/out.
• Variable nodes with 200 adjacent edges have
  been reported Richardson00

8
Solving Congestion in Hardware

• Serial architecture with groups of parallel
  optimized processing elements
• Full utilization of pipelined hardware with
  alternating blocks
• E.g. 128x parallelism in commercial IP
  (FlarionTM)
• Further memory reduction through staggered
  decoding schedule
• E. Yeo, P. Pakzad, B. Nikolic, and V.
  Anantharam, "High throughput low-density
  parity-check architectures," Proc. IEEE
  Globecom2001, San Antonio, TX, pp.3019-24, Nov
  2001.

9
Solving Congestion in Code Design

• Turbo codes comprising convolutional codes
  concatenated through interleaver
• R. J. McEliece, D.J.C. Mackay and J. F. Cheng,
  Turbo Decoding as an Instance of Pearl's Belief
  Propagation' Algorithm, IEEE Journal on Selected
  Areas in Communication, Feb. 1998, pp.140-52.
• Requires MAP (BJCR Algorithm) or Soft Output
  Viterbi decoders
• LDPC codes based on finite field geometries
• Cyclic connectivity between nodes
• LDPC codes based on Ramanujan graphs
• Hierarchical connectivity with regular local
  interconnect

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Platform vs. Throughput Summary
Platforms
11
Relative complexities
Difference in complexity 5 orders of magnitude
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Future Applications of Iterative Decoding

• 3dB Coding gain can
• Reduce transmitter power by 50
• Reduce required BW by 50
• Double throughput rate
• Reduce antenna size by 30
• Increase range by 40