Hierarchical Bottomup Analog Optimization Methodology Validated by a DeltaSigma AD Converter Design

1
Hierarchical Bottom-up Analog Optimization
Methodology Validated by a Delta-Sigma A/D
Converter Design for the 802.11a/b/g Standard

• Tom Eeckelaert, Raf Schoofs,Georges Gielen,
  Michiel Steyaert, Willy Sansen

K.U.Leuven, Belgium Department of Electrical
Engineering Division ESAT-MICAS, CAD
DAC 2006, July,San Francisco, California, USA
2
Overview

• Methodology outline
• Introduction to MOO and MOEA
• Algorithm implementation
• Experimental validation?? A/D Converter Design
  for the 802.11a/b/g standard

3
Methodology Outline The designers way
Systemspecs
Redesign
Knowledge based
Topology selection Topology sizing
Systemsimulation verification
Final Design
4
Methodology Outline The MOBU way
PickPareto-optimal design according to specs
Systemspecs
Final Design
5
Methodology outline Pareto-optimal tradeoff

• Pareto-optimal tradeoff surface
• set of designs which cannot be improved in any
  performancecharacteristic without degrading an
  other performance result.

SNR
Power
6
Methodology Outline top-down approach

• Comparison with top-down constraint-driven
  methodology

System
System Designed
Specs
7
Methodology Outline top-down approach

• Comparison with top-down constraint-driven
  methodology

System Designed
Specs
Verify
Verify
Verify
Verify
8
Methodology Outline The MOBU way
System
9
Methodology Outline The MOBU way
System
Subblock 1
Subblock 2
Subblock n
SB 1.1
SB 1.2
SB 1.m
SB 2.1
SB 1.2.1
SB 1.2.2
SB 2.2
Our work using Pareto-optimal lower-level
information
10
Overview

• Methodology outline
• Introduction to MOO and MOEA
• Algorithm implementation
• Experimental validation?? A/D Converter Design
  for the 802.11a/b/g standard

11
Introduction Multi-objective Optimization

• Definition

Genotype space X
Phenotype space Y
F(X)
12
Introduction Pareto-optimality

• Solution Set of points on a tradeoff surface
• decision vectors which cannot be improved in
  any objective without degradation in other
  objectives.
• Pareto-optimal decision vectors

SNR
Power
13
Introduction MOEA

• Multi-objective Evolutionary Algorithms
• Data structure

14
Introduction MOEA

• Algorithmic Flow

Initialization
Fitness Assignment
Selection
Recombination
Mutation
15
Introduction MOEA

• Algorithmic Flow
• InitializationA population of individualsis
  generated
• With expert knowledge
• At random

Initialization
Fitness Assignment
Selection
Recombination
Mutation
16
Introduction MOEA

• Algorithmic Flow
• Fitness Assignment
• Related to the quality of the individual
• with respect to the targets, a real-valued
• number is assigned to each individual.
• SPEA (Strength Pareto Evolutionary Algorithm)
• 
  Zitzler Thiele

Initialization
Fitness Assignment
Selection
Recombination
Mutation
17
Introduction MOEA

• Algorithmic Flow
• Selection
• Random selection of individuals to form
• a new set (Mating pool). A good fitness
• value means favored for selection.
• But all can be selected!

Initialization
Fitness Assignment
Selection
Recombination
Mutation
18
Introduction MOEA

• Algorithmic Flow
• Recombination
• From the mating pool, different pairs of
• individuals are used to recombine
• into 2 new individuals (e.g. cross-over)

Initialization
Fitness Assignment
Selection
Recombination
Mutation
19
Introduction MOEA

• Algorithmic Flow
• Mutation
• New genes are introduced into the
• population based on a stochastic process

Initialization
Fitness Assignment
Selection
Recombination
Mutation
20
Introduction MOEA benefits

• No need for determination of weighting
  coefficientslike in single-objective
  optimization.
• One optimization run immediately determines the
  Pareto-optimal solutions of a set of designs.
• Very suitable for finding optima on rough
  surfaces.
• Independent of genotypic representation.?
  possibility for heterogeneous individuals

21
Overview

• Methodology outline
• Introduction to MOO and MOEA
• Algorithm implementation
• Experimental validation?? A/D Converter Design
  for the 802.11a/b/g standard

22
Implementation Data type mapping

• e.g. simple Delta/Sigma modulator

?? individual
DACCONFIG
COMPCONFIG
FILTERCONFIG
Filter individual
Biasing
Wi
Cx
Li

23
Implementation Sorting of Pareto set

• Design space for next level up selection
  of lower-level design
• ? Sorting needed, to not lose sense of direction

8
7
5
6
2
4
3
1
24
Implementation Inter-block Constraints

• e.g. simple Delta/Sigma modulator
• interactions between sub-blocks at higher levels
• common-mode voltage, impedance matching, pole
  location
• extra design variables during lower-level
  optimization
• possible sampling schemes
• higher-level proximity selection
• lower-level discrete sampling

25
Overview

• Methodology outline
• Introduction to MOO and MOEA
• Algorithm implementation
• Experimental validation?? A/D Converter Design
  for the 802.11a/b/g standard

26
Experimental validation

• 1-bit third-order continuous-time ??-modulator
• Objective WLAN 802.11 a/b/g standard
• Conversion accuracy of 60 dB
• Signal bandwidth 10 MHz
• Sampling frequency 640 MHz ? OSR 32
• Comparison with single manual design

0.18 µm CMOS
27
Experiment Hierarchical Decomposition
?? ADC
Int 1
28
Experiment Integrator

• GmC, folded-cascode with source degeneration
• Schoofs ISCAS 2006

1.8 V

• Design variables
• biasing currents
• gate-source voltages
• transistor lengths
• gate finger width
• degeneration resistance
• integration capacitance
• common-mode voltage

0 V

• Constraint variables
• transistors in saturation

• Performance variables
• Power
• DC Gain
• Gain-bandwidth
• Phase margin

• Signal-to-noise
• Signal-to-distortion

29
Experiment Integrator

• Possible trade-off result

30
Experiment Comparator

• Comparator with 2 preamplifiers, current
  stage,and regenerative latch

1.8 V

• Design variables
• biasing currents
• gate-source voltages
• transistor lengths
• gate finger width
• load resistances
• common-mode voltage

0 V

• Constraint variables
• transistors in saturation

• Performance variables
• Power
• Regeneration speed of latch
• Offset voltage of input

31
Experiment D/A Converter

• Switched current source

• Design variables
• biasing currents
• gate-source voltages
• transistor lengths
• gate finger width
• common-mode voltage

• Constraint variables
• transistors in saturation
• pole frequency 5 x GBW

• Performance variables
• non-dominant pole frequency
• DC output impedance

32
Experiment Complete ?? modulator

• Models from lower-level building blocks, used
  forhigh-level modulator simulations
• e.g. integrator model
• ?? modulator

• Design variables
• Gain, GBW, PM, Vcm (for all integrators)
• Voffset, Speed of D/A convertor

• Constraint variables
• Inter-block constraints
• Vcm of consecutive sub-blocks
• non-dominant poles of DAC 5 x GBW of
  integrators
• ROUT DAC RIN INT

• Performance variables
• Power
• SNDR

33
Experiment Pareto-optimal trade-off

• Bounds SNDR gt 60 dB

chosen design
34
Experiment Comparison with manual design
35
Conclusions

• A Multi-Objective Bottom-Up (MOBU) design
  methodology was presented
• Multi-dimensional sorting was included to handle
  the smart selection of lower-level sub-block
  designs
• A mechanism to handle inter-block constraints was
  included to be able to combine lower-level
  sub-blocks in a higher hierarchical block
• System-level Pareto-optimal performance trade-off
  set was generated of a ?? A/D converter for
  application in the WLAN 802.11a/b/g standard.
• 25 power saving compared to the manual design
  presented in Schoofs ISCAS 2006