EE 360M Digital Systems Design Using VHDL Lecture 4

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EE 360M - Digital Systems Design Using
VHDLLecture 4

• Nur A. Touba
• University of Texas at Austin

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DELAY IN VHDL

• Two Types of Delay
• Inertial Delay
• Rejects Pulses Shorter Than Propagation Delay
• Transport Delay
• Does Not Reject Any Pulses

C lt A and B after 5ns
C lt transport A and B after 5ns
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DELAY IN VHDL

• Rejecting Short Pulses

signal lt reject pulse-width expression after
delay-time
Z3 lt reject 2 ns X after 5 ns
Equivalent to
Zm lt X after 2 ns Z3 lt transport Zm after 3 ns
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DELAY IN VHDL
Z1 lt transport X after 10 ns Z2 lt X after 10
ns Z3 lt reject 4 ns X after 10 ns
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COMPILATION AND ELABORATION
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SIMULATION

• Simulation Process
• Initialization Phase Assign Initial Values
• Actual Simulation
• VHDL Uses Discrete Event Simulation
• Passage of Time Simulated in Discrete Steps
• Statements Executed and Actions Scheduled
• Called Scheduling a Transaction
• Transaction Not Necessarily Change in Signal
  Value
• If Signal Value Changes, Called Event

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SIMULATION

• Initialization
• Initial Value Can Be Specified in VHDL Code
• If Not Specified
• Simulator Packages Will Assign Default Value
• Depending on Signal Type
• Default Initialization Not Valid for Synthesis
• Simulation Time Set to Zero
• Each Process Activated
• Schedules Corresponding Transactions

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SIMULATION EXAMPLE
A lt B or C after 2 ns D lt A after 3
ns process (A) begin E lt A or B after
1ns end process process begin C lt not C
after 3ns wait on D B lt E after
3ns end process
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SIMULATION EXAMPLE
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DELTA DELAYS

• If Zero Delay for Statement
• Simulator Uses Infinitesimal Delay, ? (delta)
• Does Not Advance Simulation Time
• Only Used for Scheduling Transactions
• ? Counter Resets when Finite Time Advances

E lt C or D C lt A or B
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EXAMPLE OF DELTA DELAYS
B lt not A C lt not B D lt not C after 5 ns
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EXAMPLE OF DELTA DELAYS
B lt A or D C lt A and not B
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SIMULATION OF MULTIPLE PROCESSES

• Model with More Than One Process
• All Processes Execute Concurrently
• Concurrent Statements Outside Processes
• Also Execute Concurrently
• Statements Inside Each Process Execute
  Sequentially
• Process Takes No Time to Execute
• Unless Has Wait Statements
• e.g., wait for 10 ns, wait for 0 ns, wait on E
• Signals Take Delta Time to Update When No Delay
  Specified

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SIMULATION EXAMPLE
architecture test1 of simulation_example is
signal A,B bitbegin P1 process(B)
begin A lt '1' A lt transport
'0' after 5 ns end process P1 P2
process(A) begin if A '1' then B lt
not B after 10 ns end if end process
P2end test1
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P1 process(B)begin A lt '1' A lt
transport '0' after 5 nsend process P1 P2
process(A)begin if A '1 then B lt
not B after 10 ns end ifend process P2
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EVENT-DRIVEN SIMULATION

• Event Change in Signal Value
• Each Time Event Occurs
• Any Processes Waiting on Event Executed in 0 Time
• Resulting Signal Changes Queued Up to Occur at
  Some Future Time
• When All Active Processes Finished Executing
• Simulation Time Advanced to Time for Next
  Scheduled Event
• Simulator Processes that Event
• Continues Until Either
• No More Events Scheduled
• Simulation Time Limit Reached

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SIMULATION EXAMPLE
B lt A process (B) begin C lt B D lt C
E lt C after 1 ns end process process begin
F lt B wait for 0 ns G lt F H lt E
after 1 ns wait on B end process
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PREDEFINED TYPES

• Predefined types
• bit '0' or '1'
• boolean FALSE or TRUE
• integer range (231 1) to (231 1)
• some implementations support wider range
• real floating-point range 1.0E38 to 1.0E38
• character any legal VHDL character
• including upper and lowercase letters, digits,
  and special characters
• printable character must be enclosed in single
  quotes, e.g., 'd', '7', ''
• time integer with units fs, ps, ns, us, ms, sec,
  min, or hr

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USER-DEFINED TYPES

• User Can Define Own Type
• Enumeration Type Very Common
• Defines Signal Called state
• Can have values S0, S1, S2, S3, S4, or S5
• Initialized to S1

type state_type is (S0, S1, S2, S3, S4,
S5) signal state state_type S1
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DATA TYPE CONVERSION

• VHDL Strongly Typed Language
• Signal and Variable Data Types Cannot Be Mixed
• Signal Assignment Only Valid If All Signals Have
  Same Types (or Closely Related)
• No Automatic Type Conversion Performed
• If Types Need to Be Mixed
• Must Perform Explicit Type Conversion
• Overloaded Operators Can Be Defined in Libraries

A lt B or C
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PREDEFINED VHDL OPERATORS

• Grouped into seven classes
• 1. Binary logical operators and or nand nor
  xor xnor
• 2. Relational operators / lt lt gt gt
• 3. Shift operators sll srl sla sra rol ror
• 4. Adding operators (concatenation)
• 5. Unary sign operators
• 6. Multiplying operators / mod rem
• 7. Miscellaneous operators not abs
•  
• When parentheses not used, operators in class 7
  have highest precedence

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EVALUATE EXAMPLE
(A not B or C ror 2 and D) 110010

• Equality test not assignment statement
• Operators Applied in Order not, , ror, or, and,
  
• Evaluate When A "110", B "111", C "011000",
  and D "111011

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OPERATORS

• Class 1 Operators and NOT Operator Applicable for
• bit, boolean, bit-vector, and boolean-vector
• Result of Relational (Class 2) Operator
• boolean (TRUE or FALSE)
• and / Operators Applicable for Almost Any Type
• Other Relational Operators Applicable to Numeric,
  Enumerated, and Some Array Types
• Example, if A5, B4, and C3
• (A gt B) AND (B lt C) evaluates to FALSE

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SHIFT OPERATORS

• Shift Operators
• Applicable for any bit-vector or boolean-vector
• If A bit-vector equal to "10010101"
• A sll 2 is "01010100" (shift left logical, '0
  fill)
• A srl 3 is "00010010" (shift right logical, '0
  fill)
• A sla 3 is "10101111" (shift left arith., right
  bit fill)
• A sra 2 is "11100101" (shift right arith., left
  bit fill)
• A rol 3 is "10101100" (rotate left)
• A ror 5 is "10101100" (rotate right)

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ARITHMETIC OPERATORS

• and Operators
• Applicable for Integer or Real Numeric Operands
• Not Defined for bit or bit-vector
• Consequently, For Full Adder
• Had to Specifically Create Carry and Sum Bits
• Several Standard Libraries Do Provide Functions
  for and That Work on bit-vectors
• Using Such library, Can Perform Addition Using

C lt A B
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ARITHMETIC OPERATORS

• Operator Used to Concatenate Two Vectors
• "010" '1' is "0101"
• "ABC" "DEF" is "ABCDEF".
• and / Operators Perform Multiplication and
  Division
• On Integer or Floating-Point Operands
• rem and mod Operators Calculate Remainder and
  Modulus for Integer Operands
• Operator Raises Integer or Floating-Point
  Number to an Integer Power
• abs Gives Absolute Value of Numeric Operand

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OVERLOADED OPERATORS

• In Standard VHDL
• Some Operations Valid Only for Certain Data Types
  
• To Apply to Other Data Types Can Use
  Overloading
• Create Overloaded Operator
• Concept of Function Overloading
• Exists in Many General-Purpose Languages
• Two or More functions Can Have Same Name
• Provided Parameter Types Sufficiently Different
  to Distinguish Which Function Intended
• Overloaded Functions Can Also Handle Operations
  Involving Heterogeneous Data Types

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VHDL LIBRARIES

• VHDL Libraries and Packages
• Extend Functionality of VHDL
• Define Types, Functions, Components, and
  Overloaded Operators
• In Early Days of CAD
• Each Vendor Created Own Libraries and Packages
• Porting Designs Became a Problem
• IEEE Developed Standard Libraries and Packages
• Make Design Portability Easier

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IEEE STANDARDS

• Original IEEE Standard
• Only Defined 2-Valued Logic (bit and bit-vector)
• IEEE.std_logic_1164
• Defines std_logic Type
• 9-Valued Logic Including 0,1,X (unknown),
  and Z (high-impedance)
• Defines std_logic_vector Type
• Vectors of std_logic Type
• Defines Logic Operations and Other Functions for
  Working with std_logic and std_logic_vector
• Does Not Provide Arithmetic Operations

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IEEE STANDARDS

• When VHDL More Widely Used for Synthesis
• IEEE Introduced Two Packages to Facilitate
  Writing Synthesizable Code
• Both Define Overloaded Logic and Arithmetic
  Operators for Signed and Unsigned Numbers
• IEEE.numeric_bit
• Uses Bit-Vectors to Represent Signed and Unsigned
  Binary Numbers
• IEEE.numeric_standard
• Uses std_logic_vectors
• First Part of Textbook Uses
• IEEE.numeric_bit Package with Unsigned Numbers
  for Arithmetic Operations

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USING LIBRARIES
library IEEE use IEEE.numeric_bit.all

• LIBRARY and USE Statements
• Must Appear in All Modules Before Entity in
  Module
• Gives Design Access to Entire numeric_bit Package

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NUMERIC_BIT PACKAGE

• numeric_bit Package Defines unsigned and signed
  Types as Unconstrained Array of Bits
• Signed Number Represented in 2s Complement Form
• Package Contains Overloaded Operators
• Arithmetic, Relational, Logical, and Shifting
• Operations on Unsigned and Signed Numbers

type unsigned is array (natural range ltgt) of
bit type signed is array (natural range ltgt) of
bit
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NUMERIC_BIT PACKAGE

• unsigned and signed are Basically Bit-Vectors
• Overload Operators Defined for These and Not
  Normal Bit-Vectors
• Compiler Error If A, B, and C are Bit-Vectors
• Must Be unsigned or signed

C lt A B
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NUMERIC_BIT PACKAGE

• Defines Overloaded Operators
• Arithmetic , -, , /, rem, mod
• Relational , /, gt, lt, gt, lt
• Logical not, and, or, nand, nor, xor, xnor
• Shifting shift_left, shift_right, rotate_left,
  rotate_right, sll, srl, rol, ror
• Acceptable Left-Right Pairs for Arith. and
  Relational
• unsigned-unsigned, unsigned-natural,
  natural-signed, signed-signed, signed-integer,
  signed-integer
• For Logical
• Both Must be signed or unsigned

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NUMERIC_BIT PACKAGE

• and Operators with unsigned Operands of
  Different Lengths
• Shortest Operand Extended by Filling 0s on Left
• Any Carry Discarded
• Result Has Same Number of Bits as Longest Operand
• Example
• 1011 110 1011 0110 0001
• Carry Discarded

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NUMERIC_BIT PACKAGE

• Overloaded Operator Provided to Add integer to
  unsigned
• But Not to Add bit to unsigned
• Carry Must Be Converted to unsigned

Sum lt A B 1 -- Allowed Sum lt A B
carry -- Not Allowed if carry type bit
Sum lt A B unsigned(0gtcarry)
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VHDL CODE FOR 4-BIT ADDER

• library IEEE
• use IEEE.numeric_bit.all
• entity Adder4 is
• port (A, B in unsigned(3 downto 0) Ci in
  bit -- Inputs
• S out unsigned(3 downto 0) Co out
  bit) -- Outputs
• end Adder4
• architecture overload of Adder4 is
• signal Sum5 unsigned (4 downto 0)
• begin
• Sum5 lt 0 A B unsigned(0gtCi) --
  adder
• S lt Sum5(3 downto 0)
• Co lt Sum5(4)
• end overload

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NUMERIC_BIT PACKAGE

• Conversion Functions
• TO_INTEGER(A)
• Converts unsigned vector to integer
• TO_UNSIGNED(B,N)
• Converts integer to unsigned vector of length N
• UNSIGNED(A)
• Causes compiler to treat bit_vector A as unsigned
  vector
• BIT_VECTOR(B)
• Causes compiler to treat unsigned vector B as
  bit_vector

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NUMERIC_STD PACKAGE

• For Multi-Valued Logic
• numeric_std Package Can Be Used
• Defines unsigned and signed as std_logic vectors
  instead of bit_vectors
• Same Set of Overloaded Operators and Functions
• Three Statements Required to Use

library IEEE use IEEE.std_logic_1164.all use
IEEE.numeric_std.all
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SYNOPSYS PACKAGES

• std_logic_arith Package from Synopys
• Popular Package for Simulation and Synthesis
• Similar to IEEE numeric_std Package
• Conversion Functions have Different Names
• Some Other Differences
• Major Deficiency
• Logic Operations Not Defined for unsigned and
  signed vectors
• Not IEEE Standard
• However, Commonly Placed in IEEE library

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SYNOPSYS PACKAGES

• std_logic_unsigned Package from Synopsys
• Does Not Define unsigned types
• Defines Overloaded Arithmetic Operators for
  std_logic_vectors
• Treat As If unsigned
• When Used with std_logic_1164 Package
• Both Arithmetic and Logical Operations Can Be
  Performed on std_logic_vectors
• 1164 Package Defines Logic Operations
• Not IEEE Standard
• However, Commonly Placed in IEEE library

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library IEEE use IEEE.std_logic_1164.all use
IEEE.std_logic_unsigned.all entity Adder4 is
port (A,B in std_logic_vector(3 downto 0) Ci
in std_logic S out std_logic_vector(3
downto 0) Co out std_logic) end
Adder4 architecture overload of Adder4 is signal
Sum5 std_logic_vector(4 downto 0) begin Sum5
lt 0 A B Ci -- adder S lt Sum5(3
downto 0) Co lt Sum5(4) end overload
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TEXTBOOK

• Uses numeric_bit Package up to Chapter 8
• Easiest to Use
• IEEE Standard
• Uses numeric_std Package Starting in Chapter 8
• Provides Multi-Valued Signals
• Similar in Functionality to numeric_bit
• Synopsys std_logic_arith and std_logic_unsigned
• Not Used
• Not IEEE Standards
• Less Functionality Than IEEE numeric_std Package