ArchitectureAware FPGA Placement Using Metric Embedding

1
Architecture-Aware FPGA Placement Using Metric
Embedding

• Padmini Gopalakrishnan
• Xin Li
• Larry Pileggi
• Electrical Computer Engineering
• Carnegie Mellon University

2
FPGAs and Regular Architectures

• Regular architectures, easy to manufacture,
  shorter turn-around times
• FPGAs, CPLDs, FPGA-like architectures
• Metal-mask or via configurable arrays of logic
• Increasing number of design starts
• Performance and sizes of these chips rapidly
  improving
• e.g., Virtex 5 550 MHz, gt 300,000 logic cells
  (not including memory and IP cores)

3
FPGAs
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FPGAs

• Complex and heterogeneous routing architectures
• Delay dominated by switches on a route
• Not geometric length
• Physical design must exploit routing architecture
• Not just minimize wirelength

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Delay Contours
Find contours of locations that have equal delay
from this location in terms of number of hops
Array of logic islands
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Delay proportional to Euclidean distance
Equi-delay Contours
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Delay proportional to Manhattan distance
Equi-delay Contours
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Delay along simple heterogeneous FPGA
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Delay along simple heterogeneous FPGA
Equi-delay Contours
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Delay along Virtex-like FPGA grid
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Delay along Virtex-like FPGA grid
Equi-delay Contours
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The Challenge and the Opportunity

• Exploit relationship between delay and routing
  grid
• Complex and FPGA-specific
• Geometric measures ? poor approximation
• Prior work tries to do this via different models
• Lookup tables Rose FPGA 00, Leaver FPGA 01
• Empirical or statistical models Bazargan DAC
  03, Karnik ICCAD 95
• Detailed delay calculation Rutenbar TCAD 98
• However .
• Lookup tables and detailed models dont scale
  well
• Empirical models depend on statistical data

13
The Challenge and the Opportunity

• FPGA placement is a discrete assignment problem

• Simulated annealing scales poorly
• e.g., VPR Rose FPL 97
• Partitioning or clustering move-based
• e.g., Selvakkumaran FPGA 04Bazargan DAC 03
  Cong FPL 04

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The Challenge and the Opportunity

• Require initial optimization that is global,
  architecture-aware, and efficient

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The Challenge and the Opportunity

• Require initial optimization that is global,
  architecture-aware, and efficient

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The Challenge and the Opportunity

• Require initial optimization that is global,
  architecture-aware, and efficient

FPGA Placement
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The Challenge and the Opportunity

• Require initial optimization that is global,
  architecture-aware, and efficient

Need new techniques cognizant of both the complex
delay model and discrete assignment nature of the
placement problem !
FPGA Placement
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Our Approach

• Placement as graph embedding into chosen metric
  space
• Metric space
• Set of objects, distance function representing
  distance between objects
• A superset of inner-product space
• First studied by Maurice Fréchet in 1906

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Our Approach

• Placement as graph embedding into chosen metric
  space
• Metric space
• Set of objects, distance function representing
  distance between objects
• Graph Embedding
• Assign coordinates to each vertex in a metric
  space
• Typically try to maintain some original notion of
  distance between vertices
• Most embeddings incur distortion

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Our Approach

• Placement as graph embedding into chosen metric
  space

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Our Approach

• Placement as graph embedding into chosen metric
  space

2 D plane
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Our Approach

• Placement as graph embedding into chosen metric
  space

2 D plane
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Our Approach

• Placement as graph embedding into chosen metric
  space

2 D plane
Most placement algorithms (e.g., QP) try to
minimize some measure of distortion
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Our Approach

• Placement as graph embedding into chosen metric
  space
• Choose appropriate metric space for FPGA routing
  grids

FPGA routing grid
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Our Approach

• Placement as graph embedding into chosen metric
  space
• Choose appropriate metric space for FPGA routing
  grids

FPGA routing grid
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Our Approach

• Placement as graph embedding into chosen metric
  space
• Choose appropriate metric space for FPGA routing
  grids

FPGA routing grid
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Our Approach

• Placement as graph embedding into chosen metric
  space
• Choose appropriate metric space for FPGA routing
  grids

Minimize distortion with respect to the FPGA
routing grid
FPGA routing grid
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Our Approach

• Placement as graph embedding into chosen metric
  space
• Choose appropriate metric space for FPGA routing
  grids
• Embedding itself is formulated as an assignment
  problem

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Overall Placement Methodology
Phase 1 Architecture-aware initial placement
solution
Phase 2 Local optimization to improve routability
and specific critical paths
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Overall Placement Methodology
Phase 1 Architecture-aware initial placement
solution
Our Focus CAPRI (Convex Assigned Placement for
Regular ICs)
Phase 2 Local optimization to improve routability
and specific critical paths
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Overall Placement Methodology
Phase 1 Architecture-aware initial placement
solution
Our Focus CAPRI (Convex Assigned Placement for
Regular ICs)
Phase 2 Local optimization to improve routability
and specific critical paths
Apply existing FPGA placement technique
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CAPRI Overview
Embed netlist graph in metric space defined by
architecture graph
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CAPRI Formulation
Location IDs (1, 2, n)
FPGA routing arch. abstracted as graph
Design netlist abstracted as graph
Define a metric space for routing architecture
Binary Quadratic Assignment Problem
Formulation Convex objective to minimize
distortion, non-convex solution space
Fast heuristic to find good assignment via matrix
decomposition and graph matching
34
CAPRI Formulation
Location IDs (1, 2, n)
FPGA routing arch. abstracted as graph
i
Design netlist abstracted as graph
Define a metric space for routing architecture
j
Binary Quadratic Assignment Problem
Formulation Convex objective to minimize
distortion, non-convex solution space
j
Fast heuristic to find good assignment via matrix
decomposition and graph matching
35
CAPRI Formulation
Logic-node IDs (1, 2, n)
FPGA routing arch. abstracted as graph
Design netlist abstracted as graph
Define a metric space for routing architecture
Binary Quadratic Assignment Problem
Formulation Convex objective to minimize
distortion, non-convex solution space
Fast heuristic to find good assignment via matrix
decomposition and graph matching
36
CAPRI Formulation
Logic-node IDs (1, 2, n)
FPGA routing arch. abstracted as graph
Design netlist abstracted as graph
Define a metric space for routing architecture
Binary Quadratic Assignment Problem
Formulation Convex objective to minimize
distortion, non-convex solution space
Fast heuristic to find good assignment via matrix
decomposition and graph matching
37
CAPRI Formulation
Logic-node IDs (1, 2, n)
FPGA routing arch. abstracted as graph
i
Design netlist abstracted as graph
Define a metric space for routing architecture
j
Binary Quadratic Assignment Problem
Formulation Convex objective to minimize
distortion, non-convex solution space
Fast heuristic to find good assignment via matrix
decomposition and graph matching
n x n
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CAPRI Formulation
FPGA routing arch. abstracted as graph
Design netlist abstracted as graph
Define a metric space for routing architecture
Binary Quadratic Assignment Problem
Formulation Convex objective to minimize
distortion, non-convex solution space
Fast heuristic to find good assignment via matrix
decomposition and graph matching
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CAPRI Formulation
FPGA routing arch. abstracted as graph
Design netlist abstracted as graph
Define a metric space for routing architecture
Assignment represented by a permutation matrix P
Binary Quadratic Assignment Problem
Formulation Convex objective to minimize
distortion, non-convex solution space
P(k,i) 1
Location k
Fast heuristic to find good assignment via matrix
decomposition and graph matching
Logic-node i
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CAPRI Formulation
FPGA routing arch. abstracted as graph
Design netlist abstracted as graph
Define a metric space for routing architecture
Assignment represented by a permutation matrix P
Binary Quadratic Assignment Problem
Formulation Convex objective to minimize
distortion, non-convex solution space
Action of P on Design Graph represented by PTDDP
Fast heuristic to find good assignment via matrix
decomposition and graph matching
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CAPRI Formulation
FPGA routing arch. abstracted as graph
Design netlist abstracted as graph
Define a metric space for routing architecture
Binary Quadratic Assignment Problem
Formulation Convex objective to minimize
distortion, non-convex solution space
Minimize Distortion
Fast heuristic to find good assignment via matrix
decomposition and graph matching
42
CAPRI Formulation
FPGA routing arch. abstracted as graph
Design netlist abstracted as graph
Define a metric space for routing architecture
Binary Quadratic Assignment Problem
Formulation Convex objective to minimize
distortion, non-convex solution space
Fast heuristic to find good assignment via matrix
decomposition and graph matching
43
CAPRI Formulation
FPGA routing arch. abstracted as graph
Design netlist abstracted as graph
Define a metric space for routing architecture
Binary Quadratic Assignment Problem
Formulation Convex objective to minimize
distortion, non-convex solution space
Fast heuristic to find good assignment via matrix
decomposition and graph matching
44
CAPRI Formulation

• Integer optimization is hard!
• Convex relaxation does not scale
• Apply series of approximations to find good
  solution

FPGA routing arch. abstracted as graph
Design netlist abstracted as graph
Define a metric space for routing architecture
Binary Quadratic Assignment Problem
Formulation Convex objective to minimize
distortion, non-convex solution space
Fast heuristic to find good assignment via matrix
decomposition and graph matching
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Implementation of CAPRI
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Implementation of CAPRI
Enables efficient distance matrix construction
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Implementation of CAPRI
Enables efficient distance matrix construction
Concurrent placement of the components Not yet
legal on the FPGA surface
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Implementation of CAPRI
Enables efficient distance matrix construction
Concurrent placement of the components Not yet
legal on the FPGA surface
Each node is legalized to a legal location on the
FPGA
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Implementation of CAPRI
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Implementation of CAPRI
Singular values of typical truncated distance
matrix
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Implementation of CAPRI

• Low-rank (k-rank) approximation of matrices
• Orthogonal iterations
• Choose k 2
• Projecting nodes and locations onto a
  k-dimensional hyperplane

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Implementation of CAPRI
Projection of Architecture Graph (simple 2D
grid) Equivalent to a 2D visualization of the
metric space of the graph
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Implementation of CAPRI
Projection of Architecture Graph (Virtex-like
grid) Equivalent to a 2D visualization of the
metric space of the graph
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Implementation of CAPRI
Projection of Design Graph (design name des) into
2 dimensions The graph itself inherently has a
higher number of dimensions
In general small k works Empirically found only
small difference between k 2, 3, and n
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Implementation of CAPRI
Nodes
Locations
Points in k-D space
Points in k-D space
Locations
Nodes
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Implementation of CAPRI
Nodes
Locations
Points in k-D space
Points in k-D space
Locations
Nodes
Bipartite Graph
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Implementation of CAPRI
Nodes
Locations
Points in k-D space
Points in k-D space
Locations

• Build bipartite graph dynamically

Nodes
Bipartite Graph
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Implementation of CAPRI
Nodes
Locations
Points in k-D space
Points in k-D space
Locations

• Build bipartite graph dynamically
• Dynamic (online) matching
• Edge costs include congestion component

Nodes
Bipartite Graph
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Experimental Highlights
Phase 1 CAPRI initial architecture-aware
placement solution
Cool anneal in VPR used for our experiments
Phase 2 Local optimization to improve
routability and specific critical paths

• Compare detailed routing results for two
  architectures
• CAPRI followed by cool anneal in VPR
• VPR alone

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Experimental Highlights
Phase 1 CAPRI initial architecture-aware
placement solution
Cool anneal in VPR used for our experiments
Phase 2 Local optimization to improve
routability and specific critical paths

• Identical placement footprints for CAPRI and VPR
  flows
• I/Os located along the periphery and placed
  simultaneously
• Delay based on smallest width of routing channel
  possible

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Delay Improvement (worst critical paths)
Minimal routing tracks (identical for both CAPRI
and VPR flows)
Simple Heterogeneous Grid
Virtex-like Routing Grid
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Delay Improvement (worst critical paths)
2 extra tracks added to elliptic
Simple Heterogeneous Grid
Virtex-like Routing Grid
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Runtime Comparison
CAPRI lt 5 of total placement runtime (even with
modest-sized problems)
Facilitates exploration
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Future Work

• Future work
• Model routing resources
• Hierarchical methodology
• Explore different options for legalization and
  local optimization
• FPGA architecture exploration and evaluation

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Acknowledgements

• Prof. Rob Rutenbar (CMU), Abhishek Ranjan
  (Xilinx), and Brian Taylor (CMU) for their
  comments
• Prof. Radu Marculescu (CMU), Dr. Ruchir Puri
  (IBM), and Steven Teig (Tabula) for their
  feedback on an early version of this work