DEPFET Thinning Technology: Closing Report on the Feasibility Study

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DEPFET Thinning TechnologyClosing Report on the
Feasibility Study
L. Andriceka, P.Fischerb, G.Lutza, M.Reiched,
R.H.Richtera, J.Treisa, M.Trimplc, N.Wermesc
aMPI Munich (HLL), bUniversity Mannheim,
cUniversity Bonn, and dMPI Halle

• Module Concept
• ThinningTechnology
• PiN Diodes on thin Silicon
• Conclusion

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Module Concept
sensitive area thinned to 50 mm, supported by a
300 mm thick frame of silicon

fully depleted electrically active back side ?
non-standard thinning technology needed
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Processing thin detectors- the Idea -
a) oxidation and back side implant of top wafer
c) process ? passivation
Top Wafer
Handle lt100gt Wafer
open backside passivation
b) wafer bonding and grinding/polishing of top
wafer
d) anisotropic deep etching opens "windows" in
handle wafer
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Module Concept- Material Budget -
Estimated Material Budget (1st layer) Pixel
area 100x13 mm2, 50 µm 0.05
X0 steer. chips 100x2 mm2, 50 µm
0.008 X0 (massive) Frame 100x4 mm2, 300 µm
0.09 X0

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Mechanical Dummies - how thin can we get?? -
window dimensions (50x13)/4 mm2 6.5x6.5
mm2 80x10.4 mm2 (80 of a tesla sensor) (50x13)/2
mm2 50x13 mm2
10 "SOI" wafers with various top layer thicknesses
24 - 29 micron (3 Wafers) 36 - 38 micron (3
Wafers) 43 - 51 micron (4 Wafers)
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Mechanical Dummies - distortions -
window dimensions (50x13)/4 mm2 6.5x6.5
mm2 80x10.4 mm2 (80 of a tesla sensor) (50x13)/2
mm2 50x13 mm2
10 "SOI" wafers with various top layer thicknesses
24 - 29 micron (3 Wafers) 36 - 38 micron (3
Wafers) 43 - 51 micron (4 Wafers)
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PiN Diodes on thin Silicon
2 types of thinned diodes
n
4 Wafers with standard Diodes as a reference

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PiN Diodes on thin Silicon
Type I pn-junction on top wafer surface
Type II pn-junction in bond region
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PiN Diodes on thin Silicon- Type I CV curves,
full depletion voltage -
50 µm, type I diode, 10 mm2
250 µm, type I diode, 10 mm2
1/C2 (104 nF-2)
1/C2 (104 nF-2)
bias voltage (V)
bias voltage (V)
C(30V) ? t 47 µm
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PiN Diodes on thin Silicon- Type I IV curves -
50 mm, 4 Type I diodes, 10 mm2
back side completely free
reverse current (pA)
reverse current (pA)
800..950 pA/cm2
700..850 pA/cm2
bias voltage (V)
bias voltage (V)
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PiN Diodes on thin Silicon- Type I IV curves -
50 µm, 4 type I diodes, 10 mm2
supporting cross over back side implant
reverse current (pA)
reverse current (pA)
800..950 pA/cm2
700..850 pA/cm2
bias voltage (V)
bias voltage (V)
module in the first layer at TESLA 13 cm2 ?
reverse current for the entire thin pixel array
would be only 11nA at full depletion!!!
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PiN Diodes on thin Silicon- Type II IV curves -
Type II Implants like DEPFET config.
Diodes of various sizes 0.09 cm2 6.5 cm2
surface generated edge current included reverse
currents at 5 V bias
900 pA/cm2
reverse current (nA)
contact opening and metallization after etching
of the handle wafer
area (cm2)
? about 4 nA _at_ 5V for the 6.5 cm2 diode,
including edge generated current
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Summary and Conclusions

• A thinning technology based on wafer bonding and
  etch back for radiation sensors with implanted
  and structured back side was presented.
• The sensitive pixel area is thinned to 50 mm and
  supported by an integrated silicon frame.
• The feasibility of the thinning technology was
  shown
• Direct wafer bonding after lithography and
  implantation is possible
• TMAH (with the appropriate additives) seems to be
  a good choice for the deep etching
• Handling of etched wafers and diced thin chips is
  safe and easy
• IV/CV measurements of diodes on thin silicon are
  extremely encouraging reverse current lt 1 nA/cm2
  for large area PiN diodes, including edge
  generated current.