Logical (or

1
Logical (or bitwise) Operations

• Manipulating bits within words
• SHIFT
• AND
• OR

2
Logical (or bitwise) OperationsSHIFT

• Moving bits within word to left or right
• In C ltlt or gtgt operators
• Example 0000 0000 0000 0000 0110 1111 0000
  0000twoshifted left by eight, equals
• 0000 0000 0110 1111 0000 0000 0000 0000two

3
Machine Instruction Format (R)
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
op basic operation (opcode) rs first register
source operand 0-31 rt second register source
operand 0-31 rd register destination operand
0-31 shamt shift amount funct function
4
MIPS Instructions (Logical)(so far)
instr format op rs rt rd shamt funct
sll R 000000 00000 reg reg amt 000000
slr R 000000 00000 reg reg amt 000010
5
Logical (or bitwise) OperationsAND and OR

• Bitwise logical AND and OR
• In C and operators
• Examples 0110 1100two 1100 0000two 0100
  0000two
• 0110 1100two 1100 0000two 1110 1100two

6
Logical AND and OR

• AND
• OR

A B C A B
0 0 0
0 1 0
1 0 0
1 1 1
a
c
b
A B C A B
0 0 0
0 1 1
1 0 1
1 1 1
a
c
b
7
MIPS Instructions (Logical)(so far)
instr format op rs rt rd shamt funct
instr format op rs rt address/immediate address/immediate address/immediate
sll R 000000 00000 reg reg amt 000000
slr R 000000 00000 reg reg amt 000010
and R 000000 reg reg reg 00000 101010
andi I 111100 reg reg immediate immediate immediate
or R 000000 reg reg reg 00000 100101
ori I 111101 reg reg immediate immediate immediate
8
Logical NOT and Multiplexor

• NOT
• Multiplexor
• (if d0, caelse cb)

A C
0 1
1 0
a
c
d
D C
0 a
a b
a
c
b
9
Arithmetic Logic Unit (ALU)

• Part of CPU
• Device implementing arithmetic (ADD, SUB) and
  logical (AND, OR) operations
• Built out of logic (AND, OR, NOT) gates and
  multiplexors
• - multiplexors are themselves built out of
  logic gates

10
The 32-bit ALU

• Built out of 32 1-bit ALUs
• 1-bit ALU
• supports 1-bit AND, OR, NOT, ADD

11
1-bit AND/OR
operation
a
result
b
12
1-bit ADD
CarryIn

a
Sum
b
CarryOut
13
1-bit ADD
Inputs Inputs Inputs Outputs Outputs Comments
a b CarryIn CarryOut Sum Comments
0 0 0 0 0 0 0 0 00
0 0 1 0 1 0 0 1 01
0 1 0 0 1 0 1 0 01
0 1 1 1 0 0 1 1 10
1 0 0 0 1 1 0 0 01
1 0 1 1 0 1 0 1 10
1 1 0 1 0 1 1 0 10
1 1 1 1 1 1 1 1 11
14
1-bit ADDCalculating CarryOut Logically

• CarryOut (b CarryIn)
• (a CarryIn)
• (a b)
• (a b CarryIn)

15
1-bit ADDCalculating CarryOut

• CarryOut (b CarryIn)
• (a CarryIn)
• (a b)

16
1-bit ADDCalculating Sum
17
1-bit ALU
operation
CarryIn
a
0
result
1
b

2
CarryOut
18
The 32-bit ALUPutting it all together (ripple
carry)
a0
b0
a1
b1
a2
b2

How long would this take to run?
a31
b31
19
1-bit SUBCalculating SUB from ADD
operation
CarryIn
Binvert
a
0
result
1
b

2
CarryOut
20
32-bit SUB

• Connect like before
• CarryOuti CarryIni1
• Binvert also tied to CarryIn on 0th unit