FrontEnd Electronics for Hybrid Pixel Detectors planar and 3D

1
Front-End Electronics for Hybrid Pixel Detectors
(planar and 3D)
SRD 2006, Trento, 14.02.2006 Giovanni Anelli -
CERN
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Outline

• SNR
• Timing resolution
• Power consumption, material budget
• Optimum partitioning
• Data rate, pile up and the substrate noise
  problem
• Radiation effects in microelectronics
• Radiation effects in silicon detectors cooling
• Layout considerations
• Summary

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Outline (2nd tentative)

• Signal, speed and noise in a Silicon Pixel
  Detector System
• Optimization for maximum Signal to Noise Ratio
• Optimization for maximum Timing Resolution
• Timing with 3D detectors
• Summary

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Outline

• Signal, speed and noise in a Silicon Pixel
  Detector System
• Optimization for maximum Signal to Noise Ratio
• Optimization for maximum Timing Resolution
• Timing with 3D detectors
• Conclusions

5
What are we after?
Signal to Noise Ratio (SNR) ? Timing resolution
? In any case, what we are interested in
is Input Signal (Detector) Speed (Detector,
Electronics) Noise (Detector, Electronics)
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The timing resolution

• The best achievable timing resolution depends on
• Electronic noise (sn_out)
• Signal slope
• Signal amplitude
• Signal speed

vout(t)
Threshold
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Silicon detector signal amplitude
The amount of charge deposited follows the Landau
distribution. Thicker detectors give more signal!
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Silicon detector speed
The carrier speed depends on the carrier type, on
the applied bias voltage and on the detector
temperature
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Silicon detector speed (2)
Signal shape example we assume an over depleted
planar detector (200 mm thick, large pixels)
E 104 V/cm
All the created electrons and holes are collected
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The beauty of 3D detectors
Thin planar detectors are fast but we loose
signal! In 3D detectors we decouple the signal
amplitude (which comes from the thickness) from
the speed (which comes from the distance between
vertical electrodes).And we have small depletion
voltages and radiation hardness. The possible
disadvantages are that the signal shape depends
on where the ionizing particle goes through the
detector and that the capacitance might be higher
than in a planar detector (if the pitch between
the vertical electrodes is small).
more later
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Electronic Noise

• I will assume in the following that the signal
  from the detector will be amplified by a charge
  amplifier.The noise deteriorating the SNR or the
  time resolution is mainly due to the noise of the
  amplifier input transistor and to the detector
  leakage current shot noise (parallel noise).
• In CMOS technologies, the transistors have mainly
  two noise components
• Channel thermal noise (white noise)
• 1/f noise
• In the following, we will express the noise at
  the input of the amplifier as an Equivalent Noise
  Charge (ENC)

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Electronic Noise (2)
CF
N.B. This holds iftp gt tcoll_holes
vout(t)
Vout_MAX
SHAPER
iin(t)
tp
CD
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Electronic Noise (3)
CF
NOTE DEPENDENCIES ON W AND tp
SHAPERtp
iin(t) Ileak
CD
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Planar detector capacitance
The detector capacitance is a function of the
detector thickness tdet and of the pixel size.
The capacitance of each pixel (Cdet) has a
component dependent on the pixel area and one on
the pixel perimeter. The latter is normally quite
important and has a very little dependence on
tdet.
Not to be forgotten parasitics!
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Detector leakage current
If the dominating component of the leakage
current comes from the bulk, the leakage current
of each pixel Ileak varies linearly with the
volume of the pixel.
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Noise vs shaping time (low Ileak)
Ileak 10 pA, Cdet 200 fF, IDS 130 mA
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Noise vs shaping time (high Ileak)
Ileak 10 nA, Cdet 200 fF, IDS 130 mA
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Noise vs transistor width
Ileak 10 nA, Cdet 200 fF, IDS 130 mA, tp
10ns
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Outline

• Signal, speed and noise in a Silicon Pixel
  Detector System
• Optimization for maximum Signal to Noise Ratio
  (planar detectors)
• Optimization for maximum Timing Resolution
• Timing with 3D detectors
• Conclusions

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Is there an optimum somewhere?
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Optimization program

• Once we have fixed
• Power available per unit area
• Detector leakage current per unit area
• Technology, transistor type and gate length
• Detector thickness
• For each pixel dimensions we have that the ENC is
  a function of the shaping time and of the
  transistor size. This function has always a
  minimum. We plot this minimum as a function of
  the pixel dimensions.
• N.B. All the calculations done in the following
  take into account the variations of Cgs and gm
  depending on the transistor working region

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Optimum pixel size (for SNR) Ex. 1

• Power 1.2 W / cm2
• tdet 150 mm
• Ileak 10 nA / cm2
• 0.25 mm TSMC technology
• PMOS input transistor, minimum gate length
• All the power per pixel BUT 500 mW goes into the
  input transistor

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Shaping time Ex. 1
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Transistor width Ex. 1
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Optimum pixel size (for SNR) - Ex. 2

• Power 1.2 W / cm2
• tdet 150 mm
• Ileak 10 mA / cm2
• 0.25 mm TSMC technology
• PMOS input transistor, minimum gate length
• All the power per pixel BUT 500 mW goes into the
  input transistor

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Shaping time Ex. 2
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Optimum pixel size (for SNR) - Ex. 3

• Power 1.2 W / cm2
• tdet 150 mm
• Ileak 10 nA / cm2
• Shaping time 25 ns
• 0.25 mm TSMC technology
• PMOS input transistor, minimum gate length
• All the power per pixel BUT 500 mW goes into the
  input transistor

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Outline

• Signal, speed and noise in a Silicon Pixel
  Detector System
• Optimization for maximum Signal to Noise Ratio
• Optimization for maximum Timing Resolution
  (planar detectors)
• Timing with 3D detectors
• Conclusions

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Timing resolution

• Obtaining a good SNR is normally NOT a problem
  with pixel detectors (except in special cases
  such as extremely small signals and very small
  power and very high granularity). Having a good
  timing resolution is a bit trickier
• Lets make some assumptions
• Max power dissipation allowed 1.2 W/cm2
• Signal Minimum of the Landau divided by 2 to
  take into account the charge sharing
• Technology considered IBM 0.25 mm CMOS (but
  similar results are obtained with the IBM 0.13 mm
  CMOS)
• We always chose the shaping time equal to the
  hole collection time (this for the best timing
  resolution)

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Optimum pixel size (for timing) Ex. 1
With a low leakage current and at short shaping
times the noise is dominated by the white noise
components.
The shaping time is here chosen equal to the hole
collection time (to go fast without loosing
signal)
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Optimum pixel size (for timing) Ex. 2
For higher leakage currents (after irradiation)
the parallel noise component (ENCp) become also
very important, as we can see in the plots at
room temperature. Only cooling down we go
(almost) back to the case in which the noise is
dominated by the white noise.
We see here the importance of cooling (if the
detector leakage current is too high). But
cooling might be difficult if we need a small
material budget.
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Optimum tdet (for timing) Ex. 1
For low leakage currents we are dominated by
white noise, which decreases increasing the
shaping time
tp increases linearly with the detector
thickness, Qin almost linearly.
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Optimum tdet (for timing) Ex. 2
For high leakage currents (like for an irradiated
detector at room temperature) increasing the
shaping time does not decrease the noise anymore!
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Outline

• Signal, speed and noise in a Silicon Pixel
  Detector System
• Optimization for maximum Signal to Noise Ratio
• Optimization for maximum Timing Resolution
  (planar detectors)
• Timing with 3D detectors
• Conclusions

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The beauty of 3D detectors

• With 3D detectors we can maximize signal and
  speed at the same time (they can be thick and
  fast at the same time, if the pitch between the
  columns is small).
• BUT
• A small pitch can lead to high capacitances (?
  high noise)
• In the following, we will try to estimate this
  capacitance and compare 3D and planar detectors
  (for speed).
• Note
• I will assume a thermal noise limited system
  (normally true at short shaping times).
• These results are preliminary, more work needs to
  be done.

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3D pixel capacitance
Pixel side 2pitch
We can have an estimate of the capacitance using
the coaxial cable formula. This seems to be a
reasonable estimate, according to some
simulations done by C. Piemonte (gratefully
acknowledged)
pitch
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4 columns per pixel
Pixel side 4pitch, C 4Ccol
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9 columns per pixel
Pixel side 4pitch, C 9Ccol
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Capacitance comparison
Columns per pixel
1
4
9
16
25

• Pitch 50 mm
• Columns radius 6 mm
• tdet 200 mm
• N.B. The 3D pixel capacitance is an overestimate

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Timing better planar or 3D?

• Pitch 50 mm
• Columns radius 6 mm
• tdet 200 mm
• 0.25 mm IBM technology
• PMOS input transistor, minimum gate length

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With one column per pixel
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With one column per pixel (2)
For relatively large pixels, the one column per
pixel approach gives better results.
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Summary

• First of all, remember that all the above
  calculations do not include
• The noise coming from the reset system
• The noise of the other transistors in the
  amplifier first stage
• This is going to make things a bit worse
• Unless we have very demanding requirements, it is
  normally possible to obtain good SNR (gt 10) with
  Hybrid Silicon Pixel Detectors
• It is going to be very difficult to have timing
  resolutions lt 100 ps with thin (200
  mm) planar detectors. 3D detectors are better in
  this respect!
• Power consumption is an issue (Sherwood would
  like problem more, and it is very much linked
  to how much material we can have.

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Summary (cont.)

• We know how to make radiation hard ICs,
  especially for total dose. For SEEs things might
  be more complicated, but still there are methods
  to get rid of these problems.
• The post-irradiation leakage current is a
  potential killer of the performance of a silicon
  pixel detector.
• The results I have shown are the BEST one can
  obtain. Many problems can make them much worse,
  such as, for example, substrate noise.
• I have concentrated my talk on a single
  transistor. Normally, there is a lot of system
  around it. Normally, it is not easy to make this
  system and to maintain the nice performance of
  the above mentioned single transistor!

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Thank you for your attention
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SPARE SLIDES
SPARE SLIDES
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Silicon detector speed (3)
If we want to collect all the charge (not to
loose signal) we do have to make the electronics
slower than the detector
E 104 V/cm
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Again on SNR (1)
The requirement on low noise given by the timing
resolution normally gives a very good SNR.
Increasing the detector thickness we increase the
input signal and decrease the noise (if the white
noise is dominant).
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Again on SNR (2)
When the parallel noise (from the leakage
current) becomes also important, the SNR still
increases for thicker detectors (the input signal
increases), but at a slower pace (the noise
decreases less or increases).
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The time walk
Signals with same shape but different amplitude
will cross the threshold at different times. This
spread can easily be a few nanoseconds.

• There are several techniques to compensate for
  this
• Zero crossing discriminators (bipolar signals)
• Time over threshold techniques
• Constant fraction discriminators

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And after the discriminator what?
To compensate for the time walk one can use t1
and t3 (TOT). t1 and t2 is even better, because
the slope for t2 is bigger and we keep the bus
busy for a shorter time (important for the
efficiency).
To measure the time one possibility is to use a
Time-to-Digital Converter (TDC) per group of
pixels. How many pixels can we connect to the
same TDC for a given efficiency?
PIXEL
PIXEL
PIXEL
TDC
PIXEL
. . . . .
PIXEL
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TDC Inefficiency
For 1 GHz total rate, 300 mm by 300 mm pixels and
a beam area of 36 mm by 48 mm the average rate
per pixel is 52 kHz. The probability of having
two pixels (connected to the same TDC) hit in a
time interval DT depends on the total number of
pixels N going to the same TDC.For a 1
inefficiency and an average rate of 52 kHz we
have
N
M. Scarpa
DT
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Data rate
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Digital noise in mixed-signal ICs

• Integrating analog blocks on the same chip with
  digital circuits can have some serious
  implications on the overall performance of the
  circuit, due to the influence of the noisy
  digital part on the sensitive analog part of
  the chip.
• The switching noise originated from the digital
  circuits can be coupled in the analog part
  through
• The power and ground lines
• The parasitic capacitances between
  interconnection lines
• The common substrate
• The substrate noise problem is the most difficult
  to solve.

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Noise reduction techniques

• Quiet the Talker. Examples (if at all possible
  !!!)
• Avoid switching large transient supply current
• Reduce chip I/O driver generated noise
• Maximize number of chip power pads and use
  on-chip decoupling
• Isolate the Listener. Examples
• Use on-chip shielding
• Separate chip power connections for noisy and
  sensitive circuits
• Other techniques depend on the type of substrate.
  See next slide
• Close the Listeners ears. Examples
• Design for high CMRR and PSRR
• Use minimum required bandwidth
• Use differential circuit architectures
• Pay a lot of attention to the layout

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Different types of substrates

• There are mainly two types of wafers
• Lightly doped wafers high resistivity, in the
  order of 10 O-cm.
• Heavily doped wafers usually made up by a low
  resitivity bulk ( 10 mO/cm) with a high
  resistivity epitaxial layer on top.

TSMC, UMC, IBM and STM (below 180 nm) offer type 1
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Substrate noise how to reduce it

• To minimize the impact of disturbances coming
  from the substrate on the sensitive analog
  blocks, we have mainly three ways
• Separate the noisy blocks from the quiet
  blocks. This is effective especially in uniform
  lightly doped substrates. For heavily doped
  substrates, it is useless to use a separation
  greater that about 4 times the epitaxial layer
  thickness.
• In n-well processes, p guard rings can be used
  around the different blocks. Unfortunately, this
  is again effective mainly for lightly doped
  substrates. Guard rings (both analog and digital)
  should be biased with separate pins.
• The most effective way to reduce substrate noise
  is to ground the substrate itself in the most
  solid possible way (no inductance between the
  substrate and ground). This can be done using
  many ground pins to reduce the inductance, or,
  even better, having a good contact on the back of
  the chip (metallization) and gluing the chip with
  a conductive glue on a solid ground plane.
• Separate the ground contact from the substrate
  contact in the digital logic cells, to avoid to
  inject the digital switching current directly
  into the substrate.

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Interaction radiation - ICs
The two most important phenomena to be considered
are ionization and nuclear displacement. Neutrons
give origin mainly to nuclear displacement. Photon
s give ionization. Charged hadrons and heavy ions
give both at the same time. For ionization we
talk about Total Ionizing Dose (TID), for nuclear
displacement about Fluence
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Interaction radiation ICs (2)
MOS
TID
Bipolars
Cumulative Effects
Bipolars
Displacement
Optoelectronics
Non Catastrophic (SEU)
Single Event Effects (SEE)
MOS
Catastrophic (SEGR, SEL)
MOS
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Radiation-hard circuits

• Using a CMOS technology we have to worry only
  about TID effects and SEEs
• In the Microelectronics Group at CERN we have
  developed layout techniques which allow solving
  the most disturbing TID effects and the Single
  Event Latch-up (SEL) issue
• Single Event Gate Rapture (SEGR) never occurs in
  advanced CMOS processes
• Single Event Upset (SEU) still remains an issue.
  We will have to protect the most critical digital
  blocks against it (special circuit architecture,
  redundancy, )

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Best option for min material budget
Readout Chip
48 mm
MATRIX32 x 60 cells
36 mm
21 mm
18 mm
Area available for all the remaining circuitry!
Detector
BUS (VDD, GND, Signals)
PROBLEMPOWER DISTRIBUTION FOR THE MATRIX, CHIP
SIZE
Support(Carbon Fiber?)
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Intermediate option
MATRIX32 x 60 cells
48 mm
18 mm
21 mm
18 mm
In this case the problem of the power
distribution is reduced but we still have a very
small area for all the rest of the circuits, a
very long chip and we have a non uniform material
budget in the centre of the beam!
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Possible best overall choice?
12 mm
48 mm
MATRIX32 x 40 cells
12 mm
18 mm

• This solution still has non uniformities in the
  material budget (but not in the beam centre). On
  the other hand it gives
• Power distribution on two sides of the chip
• More area for the circuits not in the matrix
• A smaller chip (better yield, lower cost)

Last ideaDeep Via Technology?