Achieving Reliable Ultra LowPower Digital Design with VDD Scaling

1
Achieving Reliable Ultra Low-Power Digital Design
with VDD Scaling

• Huifang Qin, Yu (Kevin) Cao, and Jan Rabaey
• Berkeley Wireless Research Center,
• University of California, Berkeley

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Outline

• Ultra-low voltage design
• Trend of supply voltage (Vdd) scaling
• Effectiveness and challenges
• Data preservation at ultra-low Vdd DRV in SRAM
• Dealing with delay variability at ultra-low Vdd
• A self-adaptive approach
• A SOC perspective
• Yield Optimization Design Approaches (YODA) group
• Summary

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Industrial Supply Voltage Scaling Trend

• Technology driven
• Effectively reduces
• design power
• consumption

(Figure courtesy of Intel)
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Scaling Scenario for Low Power Design
5.0
High Performance Scenario
3.3
3.3
Ref Davrl, et al. Proc. IEEE, April 1995
2.5
2.5
Low Power Scenario
1.8
1.5
1.5
Vdd scaling most effective approach in achieving
ultra-low power design.
1.2
1.0
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Ultra-Low Voltage Design
A design that

• Targets for ultra-low power consumption
• Aggressive voltage scaling is the premier way of
  minimizing power
• Large power reduction ratio
• Minimal design overhead in hardware / area
• Our goals design at 300 mV or below
• Is not constrained by performance (not a dominant
  factor)
• For our distributed and ubiquitous electronics
  applications, such as
• Wireless sensor networks
• Ambient intelligence
• Wearable electronics
• Is composed of unreliable components

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Power Savings at Ultra-Low Vdd
7X
9X

• Active and standby power consumptions reduce
  quadratically with Vdd scaling.

Data for 4-bit adder (0.13 mm CMOS) obtained
using Monte-Carlo simulations over process
distribution, Vth0.24V
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Price to Pay at Ultra-Low Vdd
Performance Mean Value
Performance Variance

• Delay variance at low voltages very dramatic

• Mean performance degrades exponentially below
  threshold

Concern over data storage Memory Functionality
/ Stability
Data for 4-bit adder (0.13 mm CMOS) obtained
using Monte-Carlo simulations over process
distribution, Vth0.24V
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Challenges at 0.3V Vdd Power vs. Yield
Reliability
Logic gates
300mV Vdd
Memory
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The Data-Retention Voltage (DRV) of SRAM
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SRAM DRV Sets lower limit of Vdd 250mV

• How to lower the DRV?
• Device Sizing tradeoff with cell area
• Adaptive voltage selection
• Adding redundancy and error correction

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Excessive Timing Variance at Low Vdd

• Delay variance at low voltages very dramatic
• Design for large yield means huge overhead at
  low voltages
• e.g. 3 sigma design at 250 mV means 200
  overkill over nominal
• Techniques to accommodate forvariability are
  essential

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Design Strategies to Deal with Delay Variance

• Worst-case design
• Leaves a lot of the crumbs on the table,
  especially if the delay variance is huge

• Self-timed or clockless design
• Dynamic adaptation, but inherent overhead is
  huge and result unpredictable

• Pseudo-synchronous design
• Synchronous design with a twist to accommodate
  missed clock edges (example RAZOR UMich)
• Only works over narrow range of delay variation

• Self-adapting design

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A Self-adapting Approach to Ultra-Low Voltage
Design

• Motivation Most timing variations are
  systematic, and can be adjusted for at start-up
  time using one-time calibration!
• Relevant parameters Tclock, Vdd, Vth
• Vth control the most effective and efficient
  at low voltages
• Can be easily extended to include
  leakage-reduction and power-down in standby

Vdd
Test inputsand responses
Module
TestModule
Tclock
Vbb

• Achieves the maximum power saving under
  technology limit
• Inherently improves the robustness of design
  timing
• Minimum design overhead required over the
  traditional design methodology

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A SOC Perspective

• Technique more effective when applied at module
  level versus chip level (exploits local
  correlation of process parameters)
• Maintaining globally synchronous approach under
  these circumstances is hard and not effective
• Natural candidate for Globally Synchronous
  Locally Synchronous (GALS) timing strategy

Chip Supervisor
synch.
Tclock
TM
TM

• Module performance
• (with respect to the absolute
• time reference)
• Either set by chip supervisor
• Or negotiated

asynchronous
Tclock
TM
TM
Time reference
Status white paper phase
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The YODA Group

• Yield Optimization Design Approaches Group

Goals Explore circuit, architecture, and design
strategies to achieve ultra low power consumption
and robust functionality for computing and
communication systems.
Jan Rabaey Andrei Vladimirescu Kevin
Cao Huifang Qin Ruth Wang Paul Friedberg Liang-Tec
k Pang Jonathan Tsao
Projects Robust VLSI Design Methodology SRAM
Leakage Reduction with State Preservation Reliable
Model of Computation Ultra-Low Voltage System
Design
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Thrust of Robust Design Solution
Levels
System

• Develop Self-Adapting Design Methodology
• Yield-aware platform for top-down design flow
• Clockless
• Design Robust Circuits
• Adaptive or redundant circuit design techniques
• Yield-aware optimization (Vdd, Vth, and W)
• Understand Nanometer Technology

Architecture
Arithmetic
Logic
Circuit
Technology
Stages
Testing
Operation
Fabrication
Design

• Cohesive platform for robust low-power VLSI
  system design

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Summary

• Tradeoff of Power vs. Yield Reliability forms
  the main challenge for ultra-low voltage design.
• New variation-tolerant design methodology and
  reliability-enhancing circuit / architecture
  techniques are needed.
• SRAM in deep-sleep implemented, and now heading
  for the support of higher reliability.
• A self-adapting approach with SOC integration is
  proposed in white paper.
• Goal of YODA building the future robust and
  low-cost ultra-low power design.