Chapter 3: Logic Levels and families

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Chapter 3 Logic Levels and families
Logic Design(CS33)

• Ms Veena V Desai
• Assistant Professor
• Department of Electronics and Communication
  Engineering
• Gogte Institute of Technology
• Udyambag, Belgaum-8. INDIA.
• Email karchiveena_at_yahoo.com

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Session 2

• Transistor Transistor Logic (TTL)
• Basic 2 input NAND gate
• (Diagram, operation)
• Wired Logic
• (Diagram, operation)
• Open Collector
• (Diagram, operation)
• TTL with Totem Pole
• (Diagram, operation,limitation)

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Session 2 .continued

• Three State Output TTL
• (Diagram, operation)
• Schottky TTL
• (symbol,circuit configuration,
  operation,types)

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TTL Example SN74LS00

• Recommended operating conditions
• Vcc supply voltage 5V 0.5 V
• Input voltages VIH 2V VIL 0.8V

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TTL Example SN74LS00

• Output Voltage (worst) VOH 2.7V VOL
  0.5V
• Propagation delay tpd 10-15
  ns
• Fan-out 20 TTL loads

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TTL Basic NAND Gate
iam-inverted active mode BC-forward
biased BE-reverse biased
R14k O, R21.6kO, R34k O, R41k O,
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Wired Logic

• It is possible to connect the outputs of some
  gates together to achieve the desired logic
  behaviour .
• This is called Wired Logic

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Wired Connection.

• The outputs of the two NAND gates can be Wired
  together to achieve the desired logic.
• The AND gate is implicit by the wired connection
  and is called the WIRED-AND connection

Wired Logic increases the power dissipation.
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Open Collector

• Hence open collector gates without R3 are
  available and are called open collector TTL.
• A single collector resistor called passive pull
  up resistor must be connected externally.

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Effect of Parasitic Capacitance

• Time constant for charging is R3C when o/p
  changes L to H.
• Discharging time constant is RQ3onC when o/p
  changes from H to L.
• Solution an active pull- up circuit called totem
  pole

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What is a totem pole?

• In art and history.
• Totem poles are carved and painted vertical
  logs, constructed by many northwest coast native
  american indian people. The poles display
  mythological images, animal spirits whose
  significance is their association with the
  lineage.

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Totem pole in TTL ?

• What is totem pole?
• addition of an active pull up circuit in the
  output of a gate is called totem pole.
• Why totem pole?
• To increase the switching speed of the gate
  which is limited due to the parasitic capacitance
  at the output.

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Totem Pole

• Requirement is
• R3 (small)-for output transition L to H(small RC
  time const)
• R3( large) -for output transition H to L(low
  power dissipation)

R14k O, R21.6kO, R3130O, R41k O,
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Is Wired Totem Pole Possible ?

• Disadvantage of Totem Pole- it does not permit
  wired logic.
• Q3,1 -off , Q4,2 -off
• Q3,2 -sat , Q4,1 -normal active mode
• Q3,2 goes from sat to active. VoutgtVolmax

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Three State Output TTL NAND
3rd state is called the high impedance state
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Factors Affecting Operating Speed

• Charging and discharging of load capacitances
• Use of totem-pole
• Storage time delay (getting the transistor out of
  saturation)
• Use of Schottky Transistor

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Schottky TTL Diode

• Metal to n-type semiconductor diodes.
• Involves only the flow of majority carriers.

Anode (metal)
Cathode n-type semiconductor
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Schottky TTL

• A schottky diode placed between the base and
  collector of an npn BJT results in a schottky
  transistor.

Circuit Configuration
Schottky Transistor symbo l
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Types of Schottky TTL

• (LS)TTL Low Power Schottky TTL
• (AS)TTL Advanced Schottky TTL
• (ALS)TTL Advanced Low Power Schottky TTL

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Summary (session 2)

• TTL Logic Family
• Basic TTL NAND Gate
• Wired Logic
• Standard TTL
• Open Collector (to decrease power dissipation)
• Totem-pole (to increase switching speed)
• Wired Totem-pole (not possible)

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Summary (session 2)

• Variations in TTL
• Three State TTL (with enable input)
• Schottky TTL (to decrease storage time delay)