Wireless Local Area Network Design Issues - PowerPoint PPT Presentation

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Wireless Local Area Network Design Issues

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Chip Set Partitioning and Chip Level Specification. Preliminary RFIC Design topology Trade off ... Superheterodyne Low IF down converter or Direct Conversion ... – PowerPoint PPT presentation

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Title: Wireless Local Area Network Design Issues


1
Wireless Local Area NetworkDesign Issues
Suchitav Khadanga
2
RFIC Design Flow
  • System Level Specification
  • System Analysis and Architecture Choice
  • Chip Set Partitioning and Chip Level
    Specification
  • Preliminary RFIC Design topology Trade off
  • Detailed Design Phase
  • RFIC Layout
  • Parasitic Extraction and Re simulation
  • Fabrication
  • Evaluation to Specification

3
System Level Specification
  • System Level Specification
  • System Analysis and Architecture Choice
  • Chip Set Partitioning and Chip Level
    Specification
  • Preliminary RFIC Design topology Trade off
  • Detailed Design Phase
  • RFIC Layout
  • Parasitic Extraction and Re simulation
  • Fabrication
  • Evaluation to Specification

4
Transreceiver Architecture
  • Superheterodyne Low IF down converter or Direct
    Conversion Zero IF architecture
  • Synthesizer with an on chip VCO
  • Separate chip for Power Amplifier

5
Phase Noise of Synthesizer
  • Depends primarily on the VCO
  • VCO Phase noise suffers from the Low Q of on chip
    inductors
  • Off chip passives can be used to improve the
    phase noise performance

6
Choice of Process Technology
  • CMOS
  • Bi-CMOS
  • SiGe
  • or any other

7
LAYOUT
  • Impedance Mismatch
  • Metal Lines are Transmission Lines

8
Challenges
  • Taking care of on chip parasitics
  • Providing separate grounding for RF Analog and
    digital portions to avoid noise and crosstalk
    problems
  • Integration of RF and Digital leads to EMI/EMC
    problems

9
Thanks
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