PLL Jitter Analysis

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PLL Jitter Analysis
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PLL Jitter Analysis
Adjusting the loop characteristics (wN, z)
modulates the output jitter. There exists a
minimum that depends on the noise source
characteristics1,2, Fig. (a).
Problem Noise characteristics are NOT known a
priori!
Therefore, adaptive jitter optimization is
desirable (Fig. (b))!
1 K. Lim et al., A Low-Noise Phase-Locked Loop
Design by Loop Bandwidth Optimization, IEEE J.
Solid-State Circuits, vol. 35, pp. 807-15, No. 6,
June 2000. 2 M. Mansuri et al., Jitter
Optimization Based on Phase-Locked Loop Design
Parameters, IEEE J. Solid-State Circuits, vol.
37, pp. 1375-82, No. 11, November 2002.
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PLL Circuit
3 S. Sidiropoulos et al., Adaptive Bandwidth
DLLs and PLLs Using Regulated Supply CMOS
Buffers, in Proc. 2000 IEEE Symp. on VLSI
Circuits, Dig. Tech. Papers, Honolulu, HI, June
2000, pp. 124-7. 4 M. Mansuri et al., Jitter
Optimization Based on Phase-Locked Loop Design
Parameters, IEEE J. Solid-State Circuits, vol.
37, pp. 1375-82, No. 11, November 2002.
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Jitter Estimation
Signals track jitter boundaries
5 B.-J. Lee et al., A 2.5-10 Gb/s CMOS
Transceiver with Alternating Edge Sampling Phase
Detection for Loop Characteristic Stabilization,
ISSCC Digest of Technical Papers, pp. 76-7, Feb.
2003.
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Jitter Estimation Circuitry
(a) Edge Comparison Circuit (b) VCDL stage.
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Dead-Zone Generation
Tracking of jitter distribution edges by the VCDL
outputs.
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Jitter Estimation Algorithm
Update Algorithm for Vctrl.
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Simulation Results
Sequence of jitter estimates during simulation
run.
PLL jitter estimated values vs. direct
measurements
Jitter estimate closely tracks actual jitter
value.
PLL jitter at various operating points
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Implementation
Jitter Estimation

• Circuit designed in 0.13 mm CMOS and taped out
• Expected back mid-January

PLL
DL
Driver