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Power Semiconductor Model Levels in VTB

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Title: Power Semiconductor Model Levels in VTB


1
Power Semiconductor Model Levels in VTB
  • Enrico Santi
  • Liqing Lu, Steve Pytel - USC
  • Jerry Hudgins UNL
  • Patrick Palmer Cambridge Univ.

2
Contents
  • Need for semiconductor models at various levels
    of complexity
  • Description of model levels
  • Model validation
  • Parameter extraction procedure
  • Ongoing work

3
Semiconductor Device Modeling
Objectives
To support E-ship modeling activities by
providing several levels of power semiconductor
device models in VTB and other simulation
environments.
Approach
Beginning with simple behavioral models (Level-0
and Level-1 models), the proposed model levels
move to physics-based models of various
complexity (Level-2 and Level-3 models)
Relevance/Payoff
Different levels of semiconductor device models
are made available to the system designer to
accomplish various system design tasks.
Have developed one of the most accurate
circuit-oriented IGBT and diode models currently
available
4
Need for Power Semiconductor Models
  • Power semiconductor models are needed to model
    high-power converters used in electric ship for
  • System studies
  • Electro-thermal studies
  • Trade-off studies on new devices (e.g., wide
    bandgap materials)

5
Need for Power Semiconductor Models
  • Semiconductor models allow prediction of
  • Power losses (conduction and switching)
  • Temperature rise
  • Details of switching waveforms overshoot and
    ringing needed for sizing of snubbers and clamps,
    for EMI estimation, etc.

6
Model Levels
Depending on the simulation goals a certain level
of complexity is appropriate
It is desirable to have various model levels for
a given semiconductor device
7
Model Development
  • Development of semiconductor models requires
  • Mathematical formulation of model
  • Software implementation
  • Parameter extraction procedure
  • Validation

8
Key Accomplishments
  • Defined model level classification
  • Developed models for various types of IGBTs,
    IGCTs and diodes
  • Obtained good matching with experimental
    waveforms
  • Implemented models on various platforms (VTB,
    Spice, MATLAB)
  • Developed parameter extraction procedures

9
Model Levels
  • Level-0 Ideal switch
  • Level-1 Electro-thermal Switch
  • Level-2 (Lumped) 1-D model
  • Level-3 1-D or 2-D model
  • Level-4 Finite element



X. Wang, L. Lu, S. Pytel, D. Franzoni, E. Santi,
J.L. Hudgins, and P.R. Palmer, Multi-level
device models developed for the Virtual Test Bed
(VTB), Proc. IEEE 39th Industry Applications
Society Annual Meeting (IAS'04), pp. 2528-2531,
Oct. 2004
10
Level-1 Models
  • Forward conduction current as a function of
    forward voltage drop and temperature (this allows
    estimation of forward conduction losses).
  • Off-state (forward blocking) leakage current
    included.
  • Turn-on and turn-off switching times as specified
    in data sheets.

11
Level-1 Models
  • No gating or triggering losses are calculated.
  • Breakdown voltage limits are imposed (forward and
    reverse blocking).
  • Maximum forward conduction-current limit is
    imposed.
  • Maximum junction-temperature limit is imposed.
  • Simple multi-section RC equivalent network
    included for junction temperature calculation.

12
Level-1 Model Example IGBT
Tj
13
Level-2 Models
  • 1-Dimensional (lumped) in Space.
  • Simplified Physical Description.
  • Simple Thermal Effects on Carrier Motion
    Included.
  • Uses Modified and Extended Lumped-Charge
    Technique first Developed by Ma, Lauritzen, et.al.

14
Level-2 Lumped-Charge Model IGCT
15
Level-3 Models
  • All models are 1-D, quasi 2-D or 2-D.
  • All models solve the ambipolar carrier diffusion
    equation at each point in space and time.

16
Level-3 Model Attributes
  • Based on Fourier solution initially proposed by
    Leturcq and further expanded by Palmer, Santi,
    and Hudgins.
  • All Level-3 models include temperature dependent
    effects, and are valid for junction temperatures
    from 150 to 150 oC.
  • Bandgap Energy
  • Carrier Mobilities
  • Ionized Impurity Concentration
  • Carrier Lifetimes

17
Electrical Equivalent Model
18
Model Validation
  • Experiment
  • Atlas finite element simulation
  • Physics-based model
  • Atlas and the model allow us to look at the
    physics inside the device

19
Atlas Simulation vs Experiment

VGE
IC
VCE
20
Level-3 Model vs Experiment

VGE
IC
VCE
21
Charge Profile Atlas
3.0?s
3.5?s
4.3?s
2.8?s
2.0?s
8.0?s
2.7?s
22
Charge Profile Level-3 Model
3.5?s
4.3?s
3.0?s
2.8?s
2.0?s
2.7?s
8.0?s
23
Model Development and Validation
  • Developed and validated models for IGBTs (NPT,
    PT, lateral gate, trench-gate), IGCTs and diodes

NPT-IGBT at -125C
PT-IGBT at 100C
24
Parameter Extraction Procedures
  • Two-step parameter extraction procedure for IGBTs
    with automated optimization procedure
  • Parameter extraction procedure for IGCT

Optimization
25
Ongoing Work
  • Implement level-3 diode model in VTB
  • Validate steady-state forward drop predictions of
    model
  • Study IGBT inductive turn-on (IGBT-diode
    interaction)

26
VTB Model Implementation
  • Level-3 physics-based power diode model
  • Under development in VTB with full temperature
    dependent features by employing a Fourier-based
    solution for the ambipolar diffusion equation
    (ADE) of the N-base region.
  • Besides the external electrical characteristics,
    the model can also provide internal physical and
    electrical information on the device, such as the
    junction temperature and the dynamic charge
    distribution in the base region.
  • With hierarchical device building method, device
    is composed of several function blocks pn-
    junction block, n-n junction block, Ej block and
    n-base block, which is further divided into two
    sub-blocks, RC-cell block and n-base voltage drop
    block.

27
Forward Drop Validation
Experiment
Carrier distribution comparison level-3 model,
finite element
Voltage drop comparison experiment, level-3
model, finite element
28
Journal Publications 2004/2005
  • E. Santi, X. Kang, A. Caiafa, J.L. Hudgins, P.R.
    Palmer, D. Goodwine and A. Monti, "Temperature
    effects on trench-gate punch-through IGBTs," IEEE
    Trans. Industry Applications, Vol. 40, No. 2, pp.
    472-482, March/April 2004
  • A. T. Bryant, X. Kang, E. Santi, P. R. Palmer, J.
    L. Hudgins, Two-Step Parameter Extraction
    Procedure with Formal Optimization for
    Physics-Based Circuit Simulator IGBT and PIN
    Diode Models, in press, IEEE Trans. Power
    Electronics
  • X. Wang, J.L. Hudgins, E. Santi, P.R. Palmer,
    Destruction-free parameter extraction for a
    physics-based circuit simulator IGCT model,
    accepted for publication, IEEE Trans. Industry
    Applications

29
Conference Publications (I)2004/2005
  • M.A. Khan, G. Simin, S.G. Pytel, A. Monti, E.
    Santi and J.L. Hudgins, New Developments in
    Gallium Nitride and the Impact on Power
    Electronics, Proc. IEEE Power Electronics
    Specialists Conference (PESC'05), INVITED PLENARY
    SESSION, June 2005
  • L. Lu, S.G. Pytel, A. Bryant, E. Santi, J.L.
    Hudgins, P.R. Palmer, Physical modeling of
    forward conduction in IGBTs and diodes, Proc.
    IEEE 40th Industry Applications Society Annual
    Meeting (IAS'05), accepted for publication, Oct.
    2005
  • L. Lu, S.G. Pytel, A. Bryant, E. Santi, J.L.
    Hudgins, P.R. Palmer, Modeling of IGBT resistive
    and inductive turn on behavior, , Proc. IEEE
    40th Industry Applications Society Annual Meeting
    (IAS'05), accepted for publication, Oct. 2005
  • A.T. Bryant, P.R. Palmer, E. Santi, J.L. Hudgins,
    A compact diode model for the simulation of fast
    power diodes including the effects of avalanche
    and carrier lifetime zoning, Proc. IEEE Power
    Electronics Specialists Conference (PESC'05),
    accepted for publication, June 2005
  • X. Wang, J.L. Hudgins, E. Santi, P.R. Palmer,
    Destruction-free parameter extraction for a
    physics-based circuit simulator IGCT model,
    Proc. IEEE 39th Industry Applications Society
    Annual Meeting (IAS'04), pp. 2542-2549, Oct. 2004
  • X. Wang, L. Lu, S. Pytel, D. Franzoni, E. Santi,
    J.L. Hudgins, and P.R. Palmer, Multi-level
    device models developed for the Virtual Test Bed
    (VTB), Proc. IEEE 39th Industry Applications
    Society Annual Meeting (IAS'04), pp. 2528-2531,
    Oct. 2004

30
Conference Publications (II)2004/2005
  • A. Caiafa, A. Snezhko, J. L. Hudgins, E. Santi,
    P. R. Palmer, R. Prozorov, Turn-off operation of
    non-punch-through and punch-through IGBTs at
    cryogenic temperatures, Proc. IEEE 39th Industry
    Applications Society Annual Meeting (IAS'04), pp.
    2532-2541, Oct. 2004
  • S.G. Pytel, S. Lentijo, A. Koudymov, S. Rai, H.
    Fatima, V. Adivarahan, A. Chitnis, J. Yang, J.L.
    Hudgins, E. Santi, A. Monti, G. Simin, and M.
    Asif Khan, AlGaN/GaN MOSHFET integrated circuit
    power converter, Proc. IEEE Power Electronics
    Specialists Conference (PESC'04), pp. 579-584,
    June 2004
  • S.G. Pytel, A.S. Hoenshel, L. Lu, E. Santi, J.L.
    Hudgins, P.R. Palmer, Cryogenic Germanium power
    diode circuit simulator model including
    temperature dependent effects, Proc. IEEE Power
    Electronics Specialists Conference (PESC'04), pp.
    2943-2949, June 2004
  • X. Wang, A. Caiafa, J.L. Hudgins, E. Santi, P.R.
    Palmer, Implementation and validation of a
    physics-based circuit model for IGCT with full
    temperature dependencies, Proc. IEEE Power
    Electronics Specialists Conference (PESC'04), pp.
    597-603, June 2004
  • A. Caiafa, A. Snezhko, J. Hudgins, E. Santi, R.
    Prozorov, IGBT operation at cryogenic
    temperatures non-punch-through and punch-through
    comparison, Proc. IEEE Power Electronics
    Specialists Conference (PESC'04), pp. 2960-2966,
    June 2004
  • A. Caiafa, A. Snezhko, J. Hudgins, E. Santi, R.
    Prozorov, The failure of punch-through IGBTs to
    reach forward conduction mode at low
    temperatures, Proc. IEEE Power Electronics
    Specialists Conference (PESC'04), pp. 2967-2970,
    June 2004

31
Level-1 IGBT Model
  • IGBT Level-1 model is a behavioral model
    including the following attributes in a simple
    manner
  • Forward conduction current as a function of
    forward voltage drop and temperature (this allows
    estimation of forward conduction losses)
  • Turn-on/off switching losses as a function of
    current and temperature
  • No gating or triggering losses are calculated
  • Breakdown voltage limits are imposed (forward and
    reverse blocking)
  • Maximum forward conduction-current limit is
    imposed
  • Maximum junction-temperature limit is imposed
  • Simple multi-section RC equivalent network
    included for junction temperature calculation.
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