Battling state machine complexity IAR visualSTATE

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Battling state machine complexityIAR visualSTATE

• Thomas Sporrong
• Field Application Engineer
• fae_at_iar.se
• www.iar.com

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Battling state machine complexity

• Any fool can write code that a computer can
  understand.
• Good programmers write code that humans can
  understand

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Battling state machine complexity

• 32-bit ARM/Cortex architecture bring great
  opportunities
• New tools and methodologies needed?
• This session will cover one aspect of application
  the program logic implemented as state machines

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Microcontroller projects code size
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Software development
Effort
Complexity
old method
new method
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IAR visualSTATE can help

• Design of program logic
• Simulation Formal Verification of program logic
• Debugging program logic
• Maintenance of design

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Battling state machine complexity

• C-code
• Switch (state) case STOP if (event
  S_new_target T_Floor gt Floor) then state UP
  break
• case UP if (entry) then entry
  0A_drive_up()if (event S_stop)thenentry
  1 state STOPbreakcase DOWN ...

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Battling state machine complexity
State machine

• C-code
• Switch (state) case STOP if (event
  S_new_target T_Floor gt Floor) then state UP
  break
• case UP if (entry) then entry
  0A_drive_up()if (event S_stop)thenentry
  1 state STOPbreakcase DOWN ...

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Complex?
29 states
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Complex?
7 states
29 states
Number of transitions is a more critical factor
for complexity
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From design to code
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Design to code?

• Hand coding state machines
• As complexity increases, how do I ensure that I
  capture the complete design in code?
• How do I restructure the code if I discover
  errors in the design?
• Do I even have a complete design before I code?

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From design to code!

• Automatic code generation
• Do I even have a complete design before I code?
• How do I restructure the code if I discover
  errors in the design?
• No problem regenerate the code from the updated
  design!
• As complexity increases, how do I ensure that I
  capture the complete design in code?
• No problem The code is a full representation of
  the design!
• Design and code is always in sync

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From design to code
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Simulation Validation on design model
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No dead ends? No contradictions?
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Spot a difference?
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Know for sure!
Full verification requires restrictions to the
modeling language
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Design Simulation Verification
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Design maintenance

• Documentation up to date?
• How do I verify that my changes does not
  introduce contradictions/dead ends?
• Person who did the original design might have
  left the company...

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Design maintenance

• Documentation up to date?
• How do I verify that my changes does not
  introduce contradictions/dead ends?
• Person who did the original design might have
  left the company...
• Feedback from our customers
• Using IAR visualSTATE is a key advantage when
  it comes to maintenance

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Design maintenance
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IAR visualSTATE
Automatic C or C code-generation
API
Complete Target Application
Middleware
Automatic document generation
State machine design Formal verification Simulatio
n Prototyping
Device Drivers
ARM/Cortex HW
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Model debugging on hardware?
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Model debugging on hardware!
Events and actions
Breakpoints
Full design model feedback
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Model debugging on hardware
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The full circle

• Code generation from design model
• Avoid stupid coding mistakes
• Simulation/Validation on design model
• Find errors early
• Formal model checking on design model
• Find dead-locks before they bite you
• Model debugging on target hardware
• Find remaining issues faster

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More ARM/Cortex info at www.iar.com
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More ARM/Cortex info atwww.SevensAndNines.com
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Thank you!

• Thomas Sporrong
• Field Application Engineer
• fae_at_iar.se
• www.iar.com