Level 0 trigger decision unit for the LHCb experiment Rmi CORNAT, Rgis LEFEVRE, Jacques LECOQ, Pasca

1
Level 0 trigger decision unitfor the LHCb
experimentRémi CORNAT, Régis LEFEVRE, Jacques
LECOQ, Pascal PERRETLPC Clermont-Ferrand
2
Outline

• Introduction
• I/O
• General architecture
• Algorithms (prototype)
• Prototype
• Test bench

3
L0DU

• Provides the final L0 trigger
• decision
• Decision based on L0 trigger
• processor (E/HCAL, MUON)
• RS can apply a veto
• Decision fan-out by TTC
• system

4
L0DU input/output

• Calorimeters 224b_at_40 MHz
• MUON 256b_at_40 MHz
• VETO 64b_at_40 MHz
• Total 544_at_40 MHz (2.5 Go/s)
• RSDA 16b_at_40 MHz (to Readout Supervisor)
• L0Block 32b_at_40 MHz (1024b_at_1 MHz to L1)

Standard data word - 32 bits - 8b BCID - 8b energy
5
Timing

• Fully synchronous
• Events sorted in time order
• Each data source have a fixed latency
• Not precisely known
• Minimum latency of L0DU 275 ns
• Includes output drivers and cables
• Additional latency 250 ns
• Advanced algorithms

525 ns
6
L0DU logical architecture
7
RSDA

• Decision word sent to Readout Supervisor
• 1b decision
• 12b BCID (provided by TTC)
• 1b ask for forced trigger (calibration)
• 1b timing trigger bit (time alignment)
• Timing trigger bit set to '1' when
• Positive decision for BC N
• No trigger for BC N-1, N-2, N1, N2
• No functional errors

8
L0Block

• 32 words of 32 bits
• Sent one by one for each L0 trigger
• Words sent one by one at 40 MHz
• Information for L1 trigger
• L0DU I/Os
• Decision history
• Intermediate results

9
L0DU physical architecture

• A lot of point to point connections
• External
• Internal
• Use of fpga
• High density (I/O pins, logic cells, internal
  memory) to limit connection issues
• BGA type package
• Integrated LVDS,... I/O buffers
• Single PCB (no internal connectors and cables
  if possible)
• Do not need a crate

APEX Virtex
10
Input/output format

• Use of standard connectors and cables
• Ethernet CAT5, RJ45
• Input serial LVDS (48 bits on 9 pairs or 21
  bits on 4 pairs) for lt 20 m links
• DS90LV483/4 (National Semiconductor)
• Up to 672 Gbyte/s
• Pre-emphasis feature
• DC balancing
• Tested at LAL (Orsay, France)
• Output 40 MHz LVDS

11
Algorithms (examples)

• 3 highest muon search (out of 8)
• 3 clock cycles, comparator tree
• Thresholds
• Invariant mass (muons)
• Combination between simple conditions
• Downscaling temporally relaxed conditions
• Rate division
• Acceptation

12
First prototype

• No ECS, no TTC
• I/O format 40 MHz LVDS
• 96 inputs bits, 32 outputs bits
• 5 ACEX1K100 (Altera)
• Simple but exhaustive algorithms
• Synchronization
• Trigger conditions
• Downscaling
• L0Block building (internal memory)

13
First prototype (2)
5 fpgas LVDS I/O RJ45 connectors
PCB 24.5x23.3 cm
14
First prototype architecture
1,2 partial data processing 3 final
processing and decision 4 storage 5
L0Block - 3 configuration jumpers per fpga -
few spare I/O
15
L0block
Use of internal memory pipe-line then fifo
if trigger multiplexing controlled by comb.
Logic and fsm
16
Prototype input data
17
Very simple algorithm (example)

• L0 decision positive if
•   Et of the highest electron ? electron
  threshold
• or
• Et of the highest hadron ? one hadron
  threshold
• or
• ( Et of the highest hadron ? two hadrons
  first threshold )
• and
• ( Et of the second highest hadron ? two
  hadrons second threshold )
• or
• Pt of the highest muon ? muon threshold
  
• and
• primary vertex veto multiplicity ? primary
  vertex veto threshold
• and
• Et of calorimeter veto ? calorimeter veto
  threshold

18
Downscaling
19
L0DU Report
20
RSDA

• Sent 9 BC after reception of last L0 Data word
• Available at Readout Supervisor input after 10 BC
• See timing of RSDA computation

21
L0 Block

• Ready when RSDA is ready 40 BC before L0 Trigger

ECS
22
Test bench

• Need to synchronize clock board
• Fan-out of LVDS and ECL clock signals (10-60 MHz)
• Manual start signal
• Need to stimulate memory board
• 216 64 bits 40 MHz LVDS words
• VME controlled
• C software (C/PVSS software foreseen)
• Connections Ethernet CAT5 and RJ45

23
Test bench (2)
24
Memory board
16 RJ45 VME interface 4 RAMs 64 LVDS
reversible I/O PCB 24x23.3 cm
25
Functionalities

• Parameters
• Start and end addresses
• Number of runs
• Pipe-line delay
• External synchronisation signal
• Many boards in parallel
• Software in C (LabView version also exists)
• Electrical format conversion modules can be added

26
Conclusion

• First prototyping successful
• Emphasis on test bench
• Embedded test bench foreseen
• Second prototype (Q1'2004)
• ECS
• TTC
• Up-market fpga