Contextindependent Codes for Offchip Interconnects

1
Context-independent Codes for Off-chip
Interconnects
Kartik Mohanram and Scott Rixner Rice University

• December 5, 2004

2
Modern Embedded Systems
Systems-on-a-Chip (SoC) Core
Interconnect
Data Acquisition and Connectivity Peripherals
DRAM Memory
Memory Controller
Low Power. 1 W
High Performance 10 W
System Bus
Embedded Processor(s)
Scratch Pad (I, D)
DDR 64-128 MB Power 10-18 W
SDR 16-64 MB Power 1-4 W
High Performance Apps. 10 W
Low Power Apps. 250 mW
3
Coding to Reduce Transitions

• Transform values that traverse the interconnect
• Reduce Hamming distance between successive values
• Often a one-to-many mapping that allow the
  minimum distance codeword to be selected
• Bus invert coding Stan95
• Simple, effective code
• Transfer true or complement of data, based on
  Hamming distance with previously transferred
  value
• Invert bit indicates whether or not the data is
  inverted

4
Coding Context

• Context current value on the interconnect
• Context-dependent coding
• Encoded value depends on current value
• Choose codewords to minimize switching
• Requires double-ended support
• Not supported by commodity DRAM
• Context-independent coding
• One-to-one mapping
• Choose codewords to minimize weight
• Only need single-ended support

5
Limited-weight Codes (LWCs) Stan97

• m-LWC
• All values map to codewords with at most m bits
  set
• To limit the weight, codewords are wider than
  inputs
• Perfect 4-LWC
• Encodes 8-bit data into 9-bit codewords
• Invert data if more than m bits and add invert
  bit
• All possible 9 bit values with at most 4 bits set
  are used
• Single-ended, context-independent
• Minimize switching activity by following low
  weight codewords with other low weight codewords

6
Frequency-based Codes

• Use frequency information to assign codewords
• Assign best codewords to frequently occurring
  values
• Assign bad codewords to infrequently occurring
  values
• Several possibilities
• One-hot encode most frequent values Yang04
• Remap data so frequent values have the least
  weight
• Can be single-ended, context-independent

7
Frequency-based LWCs

• Combine the two techniques
• Use a 4-LWC to encode 8-bit values
• Determine assignment using each bytes frequency
• Single-ended, context-independent
• Minimize switching, as the most frequently
  occurring values map to very low weight codewords

8
Memory Controller Architecture
Systems-on-a-Chip (SoC) Core
Data Acquisition and Connectivity Peripherals
DRAM Memory
DRAM Control (Cmd Addr)
Context Independent Decoder
System Bus
Memory Queue
Embedded Processor(s)
Context Independent Encoder
I D
Memory Controller
9
Results(More Details in Paper)
10
Conclusions

• Double-ended, context-dependent codes
• State-of-the-art 22-39 reduction in
  transitions
• Require DRAM participation!
• Frequency-based limited-weight codes
• Single-ended (no support from DRAM necessary)
• Exploit frequency information for better codes
• Competitive transition reduction
• 30.3 with individual benchmark frequencies
• 25.1 with consolidated (global) frequencies

11
Double- vs. Single-ended Codes

• Double-ended codes
• Two sided transmitter and receiver both
  participate
• Data is transmitted in encoded form
• Data is stored in original form
• Single-ended codes
• One sided only memory controller participates
• Data is encoded before being written
• Data is stored in encoded form
• Data is decoded after being read