RF and mmWave Research

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RF and mm-Wave Research

• Ali M. Niknejad
• Robert Brodersen
• BWRC 2004 Summer Retreat
• University of California at Berkeley

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Presentation Outline

• Research Focus
• 60 GHz Update
• COGUR Project
• BSIM Update

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Research Focus Areas (I)
COGUR
60 GHz WLAN
BSIM
Dynamic Radio Multistandard Operability Broad/Mult
i band Voice/Data Short/Long Range
Gb/s Data Rates Multi-Antenna Architecture Sub-100
nm CMOS
BSIM4 BSIM-SPP
Anti-Collision Radar
WLAN at 17/24/40 GHz
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Research Focus Areas (II)
Organic Transistors (with Prof. Subramanian)
FinFet Devices (with Prof. King)
BSIM
Inductor/Capacitors Active Devices Oscillators/Amp
lifiers Power Harvesting
Sub 65 nm CMOS Analog Performance Microwave
Performance
BSIM-SOI BSIM-DG
Next Generation Communication Circuits
Low Cost RFID
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60 GHz Transceiver Update

• Chinh Doan, Sohrab Emami, David Sobel
• Mounir Bohsali, Brian Limketkai,
• Sayf Alalusi, Patrick McElwee

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Why is operation at 60 GHz interesting?
57 dBm
40 dBm

• Lots of Bandwidth!!!
• 7 GHz of unlicensed bandwidth in the U.S. and
  Japan
• Europe CEPT there is an urgent need to identify
  and harmonize civil requirements in the frequency
  range 5466GHz.

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60 GHz Challenges

• High path loss at 60 GHz (relative to 5 GHz)
• Antenna array results in better performance at
  higher frequency because more antennas can be
  integrated in fixed area
• Silicon substrate is lossy high Q passive
  elements difficult to realize?
• No, the Q factor is even better at high
  frequencies with T-lines, MIM caps, and loop
  inductors (Q gt 20)
• CMOS device performance at mm-wave frequencies
• CMOS building blocks at 60 GHz
• Design methodology for CMOS mm-wave
• Low power baseband architecture for Gbps
  communication

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60 GHz CMOS Wireless LAN System
10-100 m

• A fully-integrated low-cost Gb/s data
  communication using 60 GHz band.
• Employ emerging standard CMOS technology for the
  radio building blocks. Exploit electronically
  steer-able antenna array for improved gain and
  resilience to multi-path.

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A Leap Forward for CMOS
X
Where we are now with 130 nm

• CMOS offers two orders of magnitude cost
  reduction while providing higher integration and
  reliability
• Each new process generation moves it 20-40
  higher

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60 GHz Design Methodology

• Characterize active devices
• Small-signal models for 130 nm and 90 nm CMOS up
  to 65 GHz
• Large-signal models (gain compression, mixing,
  power)
• Characterize passive devices
• transmission lines, bypass/coupling capacitors,
  varactors, chokes
• Build library of active and passive devices
• Use library to build and validate modeling
• Bandpass filters, quadrature couplers
• Verify performance of key building blocks at 60
  GHz
• filters, amplifiers, mixers, oscillators
• Investigate baseband architecture to process 1
  Gb/s
• Integrate building blocks into 60 GHz front-end
• Build integrated package antenna array (w/ VTT
  collaboration)
• Interface to analog baseband

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130-nm CMOS Maximum Gain
VGS 0.65 V VDS 1.2 V IDS 30 mA W/L
100x1u/0.13u
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mm-Wave BSIM Modeling

• Compact model with extrinsic parasitics
• DC I-V curve matching
• Small-signal S-params fitting
• Large-signal verification
• Challenges
• Starting with a sample which is between typical
  and fast
• Millimeter-wave large-signal measurements
• Noise
• 3-terminal modeling

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DC Curve Fitting
Measured and modeled IDS vs. VDS.
Measured and modeled gm vs. VGS.

• I-V measurements were used to extract the core
  BSIM parameters of the fabricated common-source
  NMOS.

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Model Extraction Small-Signal

• Extensive on-wafer S-parameter measurement to 65
  GHz over a wide bias range
• Parasitic component values extracted using a
  hybrid optimization algorithm in Agilent IC-CAP.
• The broadband accuracy of the model verifies that
  using lumped parasitics is suitable well into the
  mm-wave region.

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Large-Signal Verification

• Harmonics power measurement
• Class AB operation
• Large-Signal amplification at 60 GHz

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Transmission line design of an LNA

• How do we model these transmission lines?

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Co-planar (CPW) and Microstrip T-Lines

• Microstrip shields EM fields from substrate
• CPW can realize higher Q inductors needed for
  tuning out device capacitance
• Use CPW

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40-GHz and 60-GHz CMOS Amplifiers
11.5-dB Gain _at_ 60 GHz
18-dB Gain _at_ 40 GHz

• Design methodology is incredibly accurate!
• Power consumption 36 mW (40 GHz), 54 mW (60 GHz)
• Noise and distortion measurements in progress

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Modeling of 60-GHz CMOS Mixer

• Conversion-loss is better than 2 dB for PLO0 dBm
• IF2GHz
• 6 GHz of bandwidth

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Combining LO and RF Signals

• Branch line 90º coupler
• Long lines for phase shift
• Hi insertion loss
• Area

• Reducing t-line length

• Transistors provide some free caps!

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Couplers Simulation Results

• Should be no problem with the doughnut and bridges

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Published CMOS Circuits
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Hybrid-Analog Receiver Architecture
Proposed Baseband Architecture
Clk
Clock Rec
BBI
Timing, DFE Carrier Phase, Estimators
BBI
IF
Complex DFE
ejq
BBQ
BBQ
LOIF

• Condition the signal prior to quantization
• Phase and timing recovery, equalization in analog
  domain
• Greatly simplifies requirements on the ADC/VGA
  circuitry
• Synchronization estimators in the digital domain
• Can still use robust digital algorithms for
  synchronizaiton

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The open questions are

• Inexpensive packaging strategies
• Flip-chip bonding
• LTCC
• Noise modeling and performance
• Breakdown voltage and PA
• The system design strategy to use the 7 GHz of
  bandwidth and simplify circuit requirements
• Realizing the high level of antenna gain needed
  to provide robust links
• Aperture antennas
• Antenna arrays
• On-chip antennas?

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Conclusions

• At 130 nm, mainstream digital CMOS is able to
  exploit the unlicensed 60-GHz band
• Accurate device modeling is possible by extending
  RF frequency methodologies
• A transmission-line-based circuit strategy
  provides predictable and repeatable low-loss
  impedance matching and filtering

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COGUR Cognizant Universal Radio

• Axel Berny
• Gang Liu
• Zhiming Deng
• Nuntachai Poobuapheun

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COGUR Design Goals

• An agile dynamic radio cognizant of its
  environment
• Universal operation ensures multi-standard and
  future standard compatibility
• Cognitive behavior allows spectrum re-use,
  underlay, and overlay
• Dynamic operation allows low power (only need
  linearity and low-phase noise VCO in a near-far
  situation)
• Multi-mode PA can work in linear mode for OFDM
  and high PAR modulation schemes. Efficiency is
  maintained while varying output power

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From Super-Het to Low/Zero IF Architectures

• Today fully integrated radios are often low-IF or
  zero-IF to reduce IF SAW filters
• Receiver front-end is often integrated in a
  single chip. PA is a separate chip or module.
  Synthesizer is often a separate chip.
• These radio architectures are optimized for a
  specific standard (image rejection, linearity,
  filtering, bandwidth)
• How do we integrate 5-10 such radios into one
  wireless device?

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COGUR Transceiver

• Broadband dynamic LNA/mixer
• Wide tuning agile frequency synthesizer
• Dual-mode broadband PA with integrated power
  combining and control
• Linear VGA or attenuator
• High-speed background calibrated ADC/DAC

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COGUR Front End Specs

• Frequency 800 MHz 2.5 GHz (Cellular, WLAN,
  WPAN)
• Front-End
• LNA S21 gt 12 dB, NF lt 3 dB, IIP3 gt 0 dBm
• Passive Image Reject Mixer (20 dB), G gt-5 dB,
  NFlt12 dB, IIP3 gt 20 dBm
• Baseband analog filter 40 dB blocker
  attenuation (5th order filter)
• VGA Gain 10 70 dB, NF 5 dB, IIP3 -10 dBm,
  10 dBm
• PA Multi-mode Class A/F, peak power 250mW/500mW
• On-chip power combining with dynamic output power
  control and near constant efficiency at power
  back-off
• Synthesizer
• Frequency resolution 2.5kHz
• Phase noise lt -116dBc/Hz at 600kHz
• Settling time lt 150us
• ADC
• Resolution 10-bits
• 200 MHz Sampling Rate
• Background Calibrated

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Broadband LNA Topology

• Two Stage input matching improves bandwidth by 3x
• Input network is a Chebychev filter
• Filter termination provided by active device
• Very similar to workhorse inductively degenerated
  common source amplifier
• Noise figure optimization possible (NFmin)
• Power match almost equal to noise match

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Broadband LNA Covers 800 MHz 2.5 GHz
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Dynamic LNA Performance

• Gain gt 12 dB for bias current varying from 2 mA
  14mA
• NF lt 3 dB for bias current varying from 2 mA 14
  mA
• Input match better -9 dB for current varying from
  2mA 14m A

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Wideband Fractional-N Synthesizer

• Core VCO has a tuning range of 21 to cover
  almost any frequency band. Loop must be stable
  and low-noise over entire range.

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Broadband VCO with Switch Caps

• Core VCO employs switched capacitor tuning to
  cover over 1 GHz of tuning range with low Kvco
• Digital calibration loop keeps amplitude of VCO
  fixed over entire range

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Synthesizer Phase Noise Simulation
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Broadband VCO Layout

• A 1.8 GHz LC VCO
• 1.3 GHz Tuning Range
• Mixed-signal Amplitude Calibration
• 0.18µm CMOS
• phase noise of 104.7dBc/Hz at a 100kHz
• 3.2mA from a 1.5V supply

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TX Class A/F Dual Mode PA

• Design a power amplifier which meets requirements
  called by the next generation wireless
  communication standards while providing backward
  compatibility with existing network
• Integration fully integrated without any off
  chip components
• Long talk time maintain high efficiency over
  entire output range
• High data rate amplitude modulation requires
  high linearity

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Distributive Active Transformer

• Power combining major challenge of PA design
• Caltech work has shown that DAT is promising
  candidate for fully integrated power combining
  and matching
• Low loss transmission lines form 11 transformers
• Distributed nature allows power/efficiency
  control

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BSIM5 Beta is Here

• Brief history of BSIM
• BSIM3 Industrial standard model, regional
  threshold based model, advanced short-channel
  device physics
• BSIM4 RF modules, improved holistic noise,
  leakage currents, non-uniform doping, stress
  effect
• Problems with BSIM3/4
• Models are inherently regional (sub-threshold is
  smoothly matched to strong inversion). A lot of
  short-channel effects in VTH.
• Models are source referenced (transistor produces
  artificial discontinuity in specialized
  applications such as passive mixers)
• Possibility of negative conductance or
  capacitance
• BSIM5
• New non-VTH charge-based single-equation core
  (Q-V).
• I-V and C-V models based on Q-V core.
• Short channel / advanced process effects included
  from BSIM4
• Bulk referenced model. Smooth and continuous
  derivatives.

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Acknowledgements

• BWRC Member Companies
• DARPA TEAM Project
• SRC and member companies
• STMicroelectronics and IBM for wafer processing
  and design support
• Agilent Technologies (measurement support)
• National Semiconductor
• Qualcomm
• Analog Devices
• BSIM5 Support TI, Intel, IBM, AMD,