Onchip Negative Bias Temperature Instability Sensor using Slew Rate Monitoring Circuitry - PowerPoint PPT Presentation

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Onchip Negative Bias Temperature Instability Sensor using Slew Rate Monitoring Circuitry

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On-chip Negative Bias Temperature Instability Sensor using Slew ... Causes dissociation of Hydrogen. More traps at the interface make the transistor slower ... – PowerPoint PPT presentation

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Title: Onchip Negative Bias Temperature Instability Sensor using Slew Rate Monitoring Circuitry


1
On-chip Negative Bias Temperature Instability
Sensor using Slew RateMonitoring Circuitry
  • Amlan Ghosh
  • (aghosh_at_ece.utah.edu)
  • Dr. Rahul M. Rao, Dr. Ching-Te Chuang, Dr.
    Richard B. Brown
  • Dept. of ECE, University of Utah
  • IBM, T. J. Watson Research Center

IBM ACAS 2008
2
Stress and Recovery of PMOS
  • NBTI affects PMOS transistors when gate bias is
    negative
  • Causes dissociation of Hydrogen
  • More traps at the interface make the transistor
    slower

(a) Stress phase
(b) Recovery phase
J. Keane, T. Kim, and C.H. Kim, "An On-chip NBTI
Sensor for Measuring PMOS Threshold Voltage
Degradation", International Symposium on Low
Power Electronics and Design, Aug 2007
3
NBTI Mechanism
M. Denais, et al., On-the-fly characterization
of NBTI in ultra-thin gate oxide PMOSFETs, IEEE
International Electron Devices Meeting, pp.
109-112, December 2004.
4
NBTI R-D Model for PMOS
S. Kumar, C. Kim, S. Sapatnekar, An Analytical
Model for Negative Bias Temperature Instability,
IEEE International Conference on Computer-Aided
Design, pp. 205-210 November 2006.
5
NBTI Measurement Techniques
  • Measurement using various test structures
  • May require precise test equipment
  • Frequency degradation in a stressed ring
    oscillator
  • May not be de-coupled from PBTI effect in NMOS
  • Phase adjustments between multiple delay-locked
    loops

6
NBTI Monitor
en
Slew monitor A
Ref ROSC
out
CP
Ctrl
Slew monitor B
Str ROSC
7
Principle of NBTI Detection Circuit
Due to Str ROSC
Due to Ref ROSC
P3
PN
P2
P1
A1
Str ROSC
b
c
PR1
PR2
PR3
PRN
B1
a
out
PR1
PR2
PR3
PRN
B2
C
Ref ROSC
A2
P1
PN
P3
P2
Reset
8
Slew Rate Monitor
9
Charge Pump
10
Normalized Output Voltage of Slew Rate Monitor
with Input Signal Slew
0.42mV/ps
11
Normalized Output of Slew Rate Monitor with
Number of Input Pulses
12
Sensitivity of Slew Rate Monitor with Number of
Input Pulses
13
Conclusion
  • NBTI measurement using rise-only slew
  • Design of the NBTI monitor in IBM 65nm process
  • Multiple input pulses for greater sensitivity

14
Future Work
  • - Determine the sensitivity of the NBTI monitor
    w.r.t stress voltage
  • - Implement NBTI monitoring scheme in 65nm IBM
    process
  • - Characterize circuits in real processor
    environment

15
Thank You
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