Synthesis for CMOS/PTL Logic

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Synthesis For CMOS/PTL Circuits
Congguang Yang Maciej Ciesielski Dept. of
Electrical Computer Engineering University of
Massachusetts, Amherst
Sponsored by NSF
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Motivation

• Traditional logic synthesis (SIS)
• use factored forms, algebraic factorization
  a(bc)
• boolean formulas treated as polynomials
• F ac bc ad bd (a b) (c d)
• weak Boolean factorization capability
• F a bc (a b)(a c) . cannot be found
  easily
• good for AND/OR, difficult to identify XOR and
  MUX logic
• Our approach
• based on BDD representation of logic
• truly Boolean operations, Boolean algebra rules
  applied
• a a a, a a 0, a 1 a, a 0
  0, etc
• can easily identify XOR, MUX structures
• very fast

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BDD-based Logic Decomposition

• Observation
• BDD structure reveals functional
  decomposition.

• Identify Dominators (BDD structures)
• ? different logic decompositions

• Simple dominators
• Algebraic AND, OR, XOR decomposition
• Generalized dominators
• Boolean AND, OR, XOR decomposition
• Cofactor, single/super node
• Simple/complex MUX

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Boolean AND/OR decomposition
F a bc (a b)(a c)


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Boolean AND decomposition - example
F D Q
Q ag d e
1. Find a cut in BDD of F
2. Create divisor D (generalized dominator),
reduce D
3. Compute Q from F, minimize Q
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XOR Decomposition Role of X-dominator
General idea

• Identify a node (x-dominator) with
  complement and regular edges
• Split node function into f and f
• Compose the two parts with XOR

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MUX Decomposition
Complex MUX
Simple MUX

• Identify exactly two nodes covering all
  paths to 1, 0
• Connect one node to 1, the other to 0
• Upper portion defines control h

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Decomposition of Multiple-output Functions

• Build BDD for each output
• Decompose each BDD
• Construct factoring trees
• Identify logic sharing

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Application to CMOS/PTL Logic Synthesis

• Logic balancing
• Reduction of long transistor chains
• Fanout reduction

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Application to CMOS/PTL Logic Synthesis

• Extract XORs and MUXes during BDD decomposition

• Map the decomposed logic onto CMOS and PTL
• Preserve XORs and MUXes for PTL
• Use CMOS to provide buffering for PTL
• New technology mapping techniques needed
  (tree-based mappers are inadequate)
• Develop PTL cell library
• (with and w/out buffers)

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Preliminary Results XOR Intensive Logic

• Comparison with SIS and tsai96
• XORs after/before technology mapping
• SIS mapper used (lower cost assigned to XOR
  gates)

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Application to FPGA Synthesis

• Very fast (orders of magnitude)
• Good for rapid prototyping
• Good results in terms of logic density and wiring
  
• 30 40 improvement compared to SIS FlowMap
• Open problems
• Incremental synthesis
• Specialized decomposition specifically for FPGAs