Design of a HighThroughput LowPower IS95 Viterbi Decoder

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Design of a High-Throughput Low-Power IS95
Viterbi Decoder

• Xun Liu Marios C. Papaefthymiou
• Advanced Computer Architecture Laboratory
• Electrical Engineering and Computer Science
  Department
• University of Michigan

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IS95 Convolutional Encoding

• Used in the reverse link of IS95 CDMA system
• 256 states (8 state registers)
• Rate 1/3
• Maximum Free Distance coding

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Viterbi Decoding (VD)

• VD is optimal for convolutional codes.
• Maximum likelihood decoding scheme.
• Minimum error for additive white Gaussian noise
  channel.
• VD procedure.
• Construction of a complex graph called trellis.
• Computation of the shortest path.

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Challenge of Large-State VD Designs

• High computational complexity.
• VDs with hundreds of states require multiple Gops
  throughput, when symbol transfer rates reach
  Mbps.
• Parallel processing.
• High interconnect power dissipation.
• Complex routing among the processors.

For large-state VDs, global data transfer and
interconnect issues must be considered carefully
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Viterbi Decoder Designs
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Presentation Outline

• Viterbi decoding overview
• Our contributions
• Data transfer oriented hierarchical
  inter-processor optimization
• Intra-processor power optimization
• Chip data

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Encoding Example
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Viterbi Decoding

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VD Summary

• Each decoded symbol requires a layer of similar
  computations
• 2N edge weight computations (N of states).
• N add-compare-select (ACS) operations.
• Operations within each layer are independent.

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Viterbi Decoder Architectures
Design space number of processors used
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Viterbi Decoder Architectures
Design space number of processors used
Intermediate solutions
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Key Issues

• How many ACS processors?
• Which ACS operations are executed in each
  processor?
• Which ACS operations can be executed
  concurrently?
• In what order are the operations executed?
• Can processors be pipelined?

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Q Which operations are executed in each ACS
processor?A Operation partitioning for global
data transfer reduction
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Operation Partitioning Example
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Operation Partitioning Results

• Obtain solution by iterative bi-partitioning
  (KL).
• For 64 partitions, gt50 data transfers are
  global.
• Largest absolute reduction 4 to 32 partitions.

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Q Which operations are executed
simultaneously?A Operation packing for global
bus minimization
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Operation Packing Example
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Operation Packing

• Packing procedure for global bus minimization
• One operation from each partition in each slice
• Global data transfers within a slice done
  simultaneously
• Bus cost the number of ACS units connected
• Our heuristic
• Distribute global transfers evenly in all slices

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Operation Packing Results

• Comparison solution one bus between any two ACS
  processors
• Global buses reduction 31 on the average
• Most effective range 8 to 32 partitions

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Q In what order should operations be executed?
Q Can ACS units be pipelined? A
Non-forwarding scheduling
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Non-forwarding Scheduling
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Non-forwarding Scheduling Results

• Greedy heuristic
• Pick slice with the least dependencies first.
• Iteratively pick the next slice such that the
  upper bound of the non-forwarding pipeline depth
  derived by the chosen slices is maximized.

• Architectures with 16 or more parallel processors
  allow very limited non-forwarding pipeline depth.

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Q How many ACS processors should be used?
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Viterbi Decoder Architecture
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Processor Internal Architecture

• 16-bit datapath
• 8 pipeline stages

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Processor Level Power Reduction

• Combine precomputation and saturation arithmetic.
• If one or two operands overflow, ACS is partially
  shut off.
• No significant degradation of the decoding
  performance.

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Chip Implementation

• Design RTL Verilog
• Synthesis Design Analyzer
• Placement manual floorplan
• Routing Silicon Ensemble
• Verification gate level Verilog
• Power estimation Primepower

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Chip Summary
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Conclusion

• Design case study of a 256-state IS95 VD
• Hierarchical optimization methodology
• Global data transfer minimization
• Global bus reduction
• Non-forwarding scheduling
• Precomputation and saturation arithmetic
• Viterbi decoder
• 8 pipelined processors
• 4 global buses
• Throughput 20Mbps
• Power dissipation 450mW