TwoChannel Batch by Batch Intensity Monitor for Main Injector BBI

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Two-Channel Batch by Batch Intensity Monitor
for Main InjectorBBI
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Two-Channel BBI Device
EXT RF CLOCK
BNC Input 1 From Wall Current
BNC Input 2 From Wall Current
MDAT
EXT SYNC
TCLK
AA Marker
Analog output 2
Beam/No Beam Output signal 1
Analog output 1
Beam/No Beam Output signal 2
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BBI device location MI60
MI60004
WCM fanout
BBI
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What are the main Goals?
pbar batch

• Data at 720Hz of beam intensity for 7 different
  gates (Fast Time Plot)
• beam/no beam logic signal if beam is present
  after extraction
• Analog signal of beam intensity for selected gate

One batch to pbar, the rest to NuMI
NuMI batches
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Kicker
Main Injector Harmonics 0 82
122 208 294
380 466 588 0
Gate3 NUMI batch1
Gate4 NUMI batch2
Gate5 NUMI batch3
Gate6 NUMI batch4
Gate7 NUMI batch5
Gate8 ?NUMI batch6
Gate1 Pbar batch
Gate2 Pbar Kicker firing
Placement of gates 1 Pbar batch
Bucket 0 (Synched with RF) 2 1500
ns before NuMI Batch 1
3 NuMI batch 1 Bucket 122
4 2
208 5
3 294
6 4
380 7
5 466
8 Possible 6th NuMI batch
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Project Critical Point 1Short 5ns pulses from
WCM
94ns
Figure 1 Bunch structure and a 5 bucket gap
between batches, measured with the WCM
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Project Critical Point 2 Varying baseline
Over full cycle (1.3 secs)
Turn by turn
Figure 3 Expanded measurement of the multi batch
structure during 3 turns with the RWM. The
varying baseline is evident.
Figure 2 Varying baseline of the RWM during multi
batch mode.
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Project Critical Point 3Gates Timing
Integration gates
500-1600ns Minimum time between NuMI batch
windows 3 buckets
55ns Time between pbar and NuMI
batches 43 buckets
800ns Two main integration
gates Batch (83 x 18.8ns)
1560ns NuMI Kicker rise time 1300 -
1500ns   Maximum rise/fall time of gate
10ns
Figure 4 RW?M measurement of the multi batch
structure with the pbar batch being isolated by
larger gaps (43 buckets)
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BBI Hardware
INPUTs resistive wall current monitor
53 MHz, TCLK, RevMarker..
FPGA CYCLONE
VGA
Pulse stretcher
212MHz ADC
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Cable from Tunnel
400MHz DAC
RS232, RS485
Channels 1,2
OUTPUT
DSP SHARC
10Mbit ETHERNET
Ethernet
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Direct Sampling at 200MHz
This signal is too fast for a measurement
by 200MHz Digitizer
Samples at 200MHz
1000
(Imax-Imin )/ I 42
4ns
400
phase between beam signal and digitizer clock
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Analog Pulse Stretcher
Reduces ADC Dynamic Range requirement
Operational Amplifier
PreAmp
PA
Input
OPA
OPA

-
Output
Td 5ns cable
4ns
Spreads signal /-5ns in time so it will not be
missed by ADC At 200MHz
5ns
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Analog Pulse Stretcher Input Pulse Width 2ns
Tdelay Tsample
No phase errors
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Analog Pulse StretcherTdelay gt Tsample (20)
In Pulse 5ns
phase errors!!!
(Imax-Imin )/ I 1.6
Output
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FPGA Baseline CorrectionHow define baseline?

• it is natural for our case to define "baseline"
  as a line not containing peaks"
• It means that for base line correction algorithm
  we should use at list 2 parameters threshold
  (to detect a peak amplitude above baseline) and
  window ( to separate a slow fluctuation of base
  line signal and peak signal in time domain
  region)

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Two Step Baseline Correction Algorithm
Step1 Minimum points

• Step 1 fix the floor of signal by averaging
  the lowest signal point from a sliding set (64)
  of programmable windows (100 buckets) and use to
  define the minimum signal base line used to
  define input signal threshold
• Step 2 calculate natural baseline by
  averaging all signals points below the
  threshold

Step2Threshold
Step1 minimum signal base line
Step 1 100 bucket window
Step2 final baseline
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Two Step Baseline Correction Algorithm 23
step1 input signal minimum signal baseline
Threshold
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Two Step Baseline Correction Algorithm 23
Step2 output signal
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Two Step Baseline Correction Algorithm Hardware
Implementation

• Step1 averaging a minimum signal points inside
  programmable window

INPUT Data from RF 1 bucket Integrator 18.8ns
OUTPUT Input Data with restored MinBaseLine

Minimum signal points

Comparator
Temporary Min Value Register
Sliding Average Filter
Window
-
minimum signal baseline
Rank 64
Write new value at the end of window
Current minimum signal point inside time window
Input Pulses
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Two Step Baseline Correction Algorithm Hardware
Implementation (continued)

• Step2 averaging all signals points below
  programmable threshold

INPUT Input Data with restored MinBaseLine
OUTPUT Input Data with Restored Base line

Window Comparator
Baseline Register
Threshold
-
Input Pulses
Moving Average Filter
Final Baseline
Threshold
Rank 64
Baseline
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FPGA Design
From ADC
Intensity (gate 0)
DAC
Intensity 0
RF INT
BLC
Gate Integrator 0
Beam/No Beam
gt
Start
Stop
Mean
Threshold
TCLK
FIFO
SHARC SPORT 32bit, 10Mbit
TCLK
To SHARC DSP
Rev Marker
Start
Stop
Mean
Delay
Gate Integrator 6
RF,53MHz
PLL Multiplier
Timestamp counter
ADC CLOCK
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FPGA FUNCTIONS

• What we do in the CYCLONE
• Base Line Corrections
• Beam Intensity calculation - Multi-Turn Averaging
• Generate the correct position of the batch gates.
  It is possible to program the position of the
  gates and the beam threshold for NuMI gate
  through ACNET
• A FPGA PLL multiplier (x4) is used to
  synchronize the digitizer with the external RF or
  internal (53MHz) clock

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FPGA FUTURES

• What we do in the CYCLONE (continued)
• Ability to trigger on TCLK events
• Multi-Turn Scope Trace buffer to analyze input
  and post-processing signals (4K samples)
• 10 Mbit,32bit serial interface to SHARC DSP

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SHARC Digital Signal Processor
2MB SDRAM 48LC1M16A1
FPGA SPORT interface
FPGA IO Controller MAX7128
Front End Control VGA, ADC, DAC
ACNET, ETHERNET
SHARC 21065L
Ethernet RTL8019AS
2MB FLASH RAM AM29LV017D
RS232, RS485
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SHARCs role on BBI board

• Interface board to ACNET (OAC) via TCP/IP
• Includes remote firmware/software update
• Read/write BBI CYCLONE control registers, so
  that BBI processing can be controlled and
  monitored via network
• additional offline data processing and
  filtering ( fast time plots, base line
  corrections, FE dynamic range control by VGA,)

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SummarySignal Processing Steps

• 1) Analog pulse stretcher
• 2) Digitizing by 12 bit ADC at 53x4212MHz
• 3) FPGA base line correction
• FPGA gate intensity calculation
• FPGA Multiturn Averaging
• FPGA Beam/NoBeam checking
• Scope Trace Buffers for all gates
• SHARC signal processing, FTP calculation
• SHARC TCP/IP data transfer to OAC

Inside FPGA
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SUM of Gates Intensity Fast Time Plot
FPGA Constructed Total Intensity
Full NuMI Cycle
Gates Intensity
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Gates Intensity Fast Time Plot 23 1.9 e13
NuMI Cycle
Gates (Batches)
0 1 2 3 4 5 6
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Batch by Batch Intensity 23
stacking batch
slip stack batch
Numi veto buckets (no beam just before NuMI
extraction
NuMI Batches
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21 Cycle
stacking batch
slip stack batch
Numi veto buckets (no beam just before NuMI
extraction
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BBI LabView Interface
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BBI ACNET General page
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BBI ACNET page for channel 1
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BBI ACNET page for channel 2