Task IV. Integrated InputOutput Interconnections

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Task IV. Integrated Input/Output Interconnections
Paul A. Kohla, Kevin P. Martina, (Task Leaders)
Mark G. Allena, James Castracanec, Thomas K.
Gaylorda, Dennis Hessa, David Keezera, Joy
Laskara, Gary S. Maya, James D. Meindla, Serge
Oktyabrskyc Eugene Rymaszewskib, Suresh
Sitaramana and C. P. Wonga
a Georgia Institute of Technology Atlanta, GA b
Rensselaer Polytechnic Institute Troy, NY c
University at Albany Albany, NY
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Introduction
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Interconnects - Hierarchy Continuum
3-D
Chip-Chip Interconnects
System Level

• Interconnect Methods
• Electrical
• RF
• Optical

System Module
System Level Interconnects
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Integrated Input/Output Interconnect Research
Strategy

• Extreme High Density Compliant Interconnections
• RF-based Interconnect Networks
• Optical Interconnects
• Lower Temperature Materials and Processes
• Wafer-Level Fabrication of All Interconnect
  Approaches
• Wafer Level Test and Burn-In

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Sea of Leads Motivation and Justification
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• If I/O Were an Abundant Resource
• Power Supply
• Power supply voltage drop can be reduced with
  large number of P/G input-output.
• Extra-connects Enabled by Sea-of-Leads
• Time-of-flight interconnect can be achieved by
  use of high quality wires in substrate.
• Global Clock Distribution
• Low-loss PWB transmission lines.
• Smaller clock skew.
• Off-chip Components
• High-quality discrete components embedded in PWB
  enhance mixed-signal performance.
• AC/DC Test and Burn-in
• I/O dedicated to wafer level test and burn-in
• Facilitate direct access to various cores.

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Z-axis compliant I/O
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Sea of Leads (SOL) FEA Strip Modeling
Equivalent plastic strain of lead
Equivalent plastic strain after cooling down from
reflow temperature (183 C) to room temperature
(25 C)
Von Mises Stress of Lead
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One-Turn Helix (OTH) - Thermo-Mechanical
Performance
Von Mises stress
Accumulative plastic strain

• MIL-STD-883 Thermal Cycle
• Effective plastic strain range is 0.00335
• Approximate 1800 cycles

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Novel, Low-Temperature Processes Enabling Direct
Attachment
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CTE Mismatch limits choice of materials and I/O
pitch

• Demonstration Variable Frequency Processing
• Continuous sweep through frequencies for uniform
  energy and distribution.
• Charging and arcing problems eliminated

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Curing High Temperature Materials
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Summary

• First demonstration curing of high temperature
  polymer (high performance polyimides and BCB at
  low temperature via microwave curing) with
  metals.
• Enables multi-layering and assembly of CTE
  mismatched materials at temperatures where CTE
  mismatch will not cause problems.

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Electroplating Bonding

• Form flexible (or standard) interconnect on one
  substrate and landing pads on the other substrate
• Alignment using plated guide structures
• Reimmersion in plating bath to join interconnect
  forms low resistance, mass-formed vertical array
• Repair/rework possible by appropriate
  metallurgical choices

25x25 Cu-Cu interconnect array
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Wafer-Scale Optical I/O
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FOCUSING, PREFERENTIAL - ORDER GRATING COUPLER -
VOLUME GRATING DEVICE
First design, fabrication, and testing of
diffractive coupler that have both
preferential-order and focusing characteristics
simultaneously.

• First demonstrated at Georgia Tech
• S. M. Schultz, E. N. Glytsis, and T. K. Gaylord,
  Optics Letters 24,1708 (1999).

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PHASE MASK FOR PARALLELFABRICATION OF OPTICAL
COUPLERS
A unique phase mask concept has been proposed for
wafer-scale fabrication of fabrication of optical
couplers.

• T. K. Gaylord, E. N. Glytsis, and J. D. Meindl,
  Phase mask consisting of an array of multiple
  diffractive elements for simultaneous accurate
  fabrication of large arrays of optical couplers
  and method of making same, U.S. Patent Office
  Provisional Patent No. 60/201,639 filed May 3,
  2000 U.S. Patent and PCT application filed May
  3, 2001.

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Wafer-Level Test and Burn-in Enabled by Compliant
I/O
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Interconnect Focus Center Electrical Test
Development
Approach Utilize compliant nature of I/O
leads to serve as probes for
electrical test Develop strategies that take
advantage of the available
high I/O count Develop approaches that permit
testing at the wafer level with
a high degree of parallelism
Investigate test techniques for wafer-level
burn-in
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Cost trade-off for DRAM example
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Terabit-per second test application
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Research Test Vehicle

• Large scale I/O Reseach Vehicle with Intel
• Air-cavities formed at lower temperatures and
  with different dielectric materials
• Photosensitive air-cavity materials for
  3-dimensional air-cavities
• New concepts and structures for compliance
• Reliability testing, modeling and prediction

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Research Vehicle Phase II Advanced High
Performance Substrate Technology with PRC

• Develop very high density board
• technology approaching BEOL pitch
• Air-isolation for electrical and optical channels
  within board
• Advanced, no-underfill attachment reducing CTE
  problems
• Wafer scale packaged and tested devices