EECSCS 370

1
EECS/CS 370

• Basic Processor Design
• Lecture 9

2
LC2K1 Processor as FSM
Implement transition functions (using a ROM
and combinatorial circuits)
Inputs
Outputs
Current state
Memory
Register file
Next state
3
Pentium Processor Die

• State
• Registers
• Memory
• Control ROM
• Combinatorial logic

REG
4
One possible datapath implementation for LC2K1
Instruction memory
Register file
Data memory
PC
M U X
M U X
M U X
M U X
En
R/W
En
Control ROM
3x8 decoder
5
Executing an ADD instruction on this LC2K1
datapath
Instruction memory
Register file
0 0 1
Data memory
0 1 0
PC
M U X
0 1 1
M U X
M U X
M U X
En
R/W
En
0 0 0
add 1 2 3
3x8 decoder
1
1
1
1
0
0
?
6
Executing a NAND instruction on this LC2K1
datapath
Instruction memory
Register file
0 0 1
Data memory
0 1 0
PC
M U X
0 1 1
M U X
M U X
M U X
En
R/W
En
0 0 1
nand 1 2 3
3x8 decoder
1
1
1
1
1
0
?
7
Executing a LW instruction on this LC2K1 datapath
0011001
Instruction memory
Register file
0 0 1
Data memory
PC
M U X
0 1 0
M U X
M U X
M U X
En
R/W
En
0 1 0
lw 1 2 25
3x8 decoder
0
0
1
0
0
1
0
8
Executing a SW instruction on this LC2K1 datapath
0011001
Instruction memory
Register file
0 0 1
Data memory
0 1 0
PC
M U X
M U X
M U X
M U X
En
R/W
En
0 1 1
sw 1 2 25
3x8 decoder
?
0
0
0
1
1
?
9
Executing a BEQ instruction on this LC2K1 datapath
0011001
Instruction memory
Register file
0 0 1
Data memory
0 1 0
PC
M U X
M U X
M U X
M U X
En
R/W
En
1 0 0
beq 1 2 25
3x8 decoder
?
?
0
1
?
0
?
10
Executing a BEQ instruction on an improved LC2K1
datapath
0011001
Instruction memory
Register file
0 0 1
Data memory
0 1 1
PC
M U X
M U X
1
M U X
M U X
En
R/W
En
1 0 0
beq 1 3 25
3x8 decoder
?
?
0
1
?
0
?
11
So Far, so good

• Every architecture seems to have at least one
  ugly instruction.
• JALR doesnt fit into our nice clean datapath
• To implement JALR we need to
• Write PC1 into regB
• Move regA into PC
• Right now there is
• No path to write PC1 into a register
• No path to write a register to the PC

12
Executing a JALR instruction on an improved LC2K1
datapath
Instruction memory
Register file
0 0 1
Equal
Data memory
PC
M U X
0 1 1
M U X
0
M U X
M U X
En
R/W
En
1 1 0 1
Eq
1 0 1
jalr 1 3
3x8 decoder
1
?
?
0
?
0
0
13
Special Case Executing a JALR 1 1 instruction on
an improved LC2K1 datapath
Instruction memory
Register file
0 0 1
Equal
Data memory
PC
M U X
0 0 1
M U X
0
M U X
M U X
1 0 1
En
R/W
En
1 1 0 1
Eq
1 0 1
jalr 1 1
3x8 decoder
1
?
0
?
0
1
?
0