An Overview of UltraWideband Research at Berkeley - PowerPoint PPT Presentation

1 / 29
About This Presentation
Title:

An Overview of UltraWideband Research at Berkeley

Description:

An Overview of UltraWideband Research at Berkeley – PowerPoint PPT presentation

Number of Views:46
Avg rating:3.0/5.0
Slides: 30
Provided by: ianmikest
Category:

less

Transcript and Presenter's Notes

Title: An Overview of UltraWideband Research at Berkeley


1
An Overview of Ultra-Wideband Research at Berkeley
  • Ian ODonnell, Mike Chen, Stanley Wang, Bob
    Brodersen
  • University of California, Berkeley

2
Project Areas
  • Integration of UWB transceiver in CMOS
  • System simulations
  • Complete transceiver design
  • Antenna LNA baseband gain Pulser
  • A/D
  • Digital baseband
  • Realtime simulation of UWB systems
  • BEE FPGA array
  • UWB frontend
  • Spatial Channel Measurements

3
UWB Integrated Transceiver Project
Targeting Sensor Network Application
  • Specifications
  • 100kbps over 10m with 10-3 BER
  • 1mW total (TXRX) power consumption
  • 0-1GHz bandwidth

First All-CMOS Integrated UWB Transceiver Aggressi
ve Low-Power Design Mostly-Digital approach,
simplify analog front-end Provide Flexible
Platform for Further Research
4
Flexibility for UWB system design exploration
  • Different antennas (with impedance matching to
    the LNA)
  • Variable transmit power
  • Variable pulse rates
  • Digital back-end will contain a programmable
    pulse-matched filter
  • Adjustable data recovery/synchronization blocks
  • Independent synchronization and data PN sequences
  • I/O to send the A/D data directly to an external
    digital backend (i.e. BEE) for more sophisticated
    signal processing.

5
UWB Transceiver Prototype
Goal Tape-out Single-Chip Transceiver by end of
Summer
PMF
Data Recovery Synch Detect And Tracking
GAIN and FILTERING
S/H
A/D
CLK GEN
CONTROL
PULSE
6
Antenna-LNA Co-design
7
UWB Antenna
  • UWB antenna for indoor wireless applications
  • Broadband
  • Omni-directional
  • Small size
  • Small size -- Narrowband
  • Antenna Q (?3)/(antenna size)
  • Almost impossible to have 50ohm radiation
    resistance over the whole bandwidth
  • Small size -- Omni-directional
  • Phase difference on the antenna is small

6cm Dipole Antenna Input Impedance
Resistance
Reactance
Reactance Dominates!
8
Small Antenna Modeling
Take small Loop Antenna as an example
  • E-fields in all directions are with almost the
    same waveform
  • Only one resistor in our model
  • By superposition, waveform across Rrad is equal
    to the far-zone E-fields
  • Can estimate radiated E-field in SPICE

9
RX LNA
Desirable Functionality
  • Gain 10 V/V over 1GHz BW
  • Noise Figure lt 10dB (Not Critical In an
    Interference Dominated Environment)
  • Differential Input
  • Handle Multiple Antennas (I.e. Current Loop
    and/or Dipole)
  • Switch Bias On/Off within TWINDOW
  • Fast Overload Recovery (Track Full- Scale 1GHz
    Sinusoid)

-

-

Implementation
May Build Two Amplifiers and Selectively
Connect/Enable for Experimentation
10
Current-Reuse Technique
Shunt-Feedback
Common-Gate
  • PMOS are added in as amplifying devices
  • No extra DC current
  • Gm gmn gmp
  • Rin is halved
  • Voltage gain is doubled
  • NF decreased by 3dB
  • BW decreased but OK

Rin 1/(gmngmp) Rin,diff 2/(gmngmp)
Rin 1/(gmngmp) Rin,diff 2/(gmngmp)
11
UWB LNA Layout w/o Capacitors
Mb1 Mb2
  • ST Microelectronics 0.13um CMOS triple-well
    process
  • Layout area
  • 59um x 45um
  • Common-centroid layout for good transistor
    matching
  • Dummy for good resistor matching
  • Capacitors off-chip

Mp1
Mp2
Rf2
Mp1
Mp2
Rf1
59um
Mn2
Mn1
Mb3 Mb4
Mn2
Mn1
45um
12
CMOS Analog Frontend
13
Transceiver Analog Front-End
  • Focus
  • Low voltage, low power CMOS circuit design with
    few external passives (I.e. crystal)
  • Accurate, flexible, controllable pulse
    reception window
  • Antenna/circuit co-design
  • Status
  • Design Nearly Complete
  • Some Layout Done
  • Tape-out in Summer

14
Pulse Reception
Parallel Sampling of Window of Time
time
TSAMPLE
TWINDOW
TPULSE_REP
time
Three Clocking Timescales TSAMPLE (ltns)
TWINDOW (10s ns) TPULSE_REP (100s ns)
15
Oscillator Accuracy (Matching)
10
Precision Component
0.1 1000 PPM
Crystal
10 PPM
TCXO
Drift lt 25ps Over Symbol
16
Oscillator Precision (Jitter)
RMS Jitter lt 25ps Over Symbol
Ring Oscillators
LC Oscillators
17
Spectrum Usage
Interferers TV 174-216MHz, 470-806MHz ISM
902-928MHz, 2.4-2.4835GHz, 5.725-5.850GHz Cell
phone824-849MHz, 870-893MHz Pager
929-930MHz PCS 1.85-1.99GHz Microwave Oven
2.45GHz
18
A/D Bitwidth
1-bit A/D Is Adequate
Interference Dominates (Noise Figure Not
Critical)
19
RX A/D Comparator requirement
1-Sigma VOFFSET for Fixed Tracking BW1GHz
1000
100
VOFFSET (mV)
10
VOFFSET 20mV (w/ No Explicit Cancellation) for
CSAMPLE gt 10fF
1
1
1000
100
10
CSAMPLE (fF)
20
UWB RX Baseband
21
Transceiver Digital Back-End
Process 0.13um (ST Microelectronics) Size 3.3mm
x 3.3mm 245,000 Standard Cells Status In
Place-and-Route Stage
22
Processing Gain
  • Input Eb/No is -11dB. Results show 1024 chips is
    enough.
  • (1) Acquisition mode, 400 chips is enough for
    suppressing the acquisition error below 1e-3.

(2) Data recovery mode, 100 chips could achieve
an uncoded bit error rate of 1e-3.
 
23
Parallel v.s. Serial Acquisition
  • Assume the worst case using 1024 PN chips, while
    pulse rate is equal to 100 ns. We need to choose
    somewhere in between.

(1) Acquisition Time
(2) Area Cost
Fully Parallel (500 mm2)
Serial (0.1sec)
Fully Parallel (0.1 ms)
Serial (5.8 mm2)
24
Operation Mode - Tracking
25
Area and power estimation
26
Pulse Transmitter
27
UWB Pulser/Antenna Co-design
  • Large Current Radiator (LCR) as the UWB antenna
  • Notch filter for FCC radiation mask
  • H-bridge pulser to drive inductive load
  • Flexible driving force by parallel structure

28
H-bridge Simulation Results
  • Doublet is generated
  • Pulse-width 1nS
  • Smoothed after low-pass filtering at the receiver
  • Meet FCCs rule
  • EIRP will increase when PRF(Pulse Repetition
    Freq) increases

VRrad
FCC Mask
Vfiltered
EIRP (dBm/MHz)
Time(ns)
Frequency (GHz)
29
Driver Circuit Layout
  • STMicroelectronics 0.13um CMOS process
  • Chip area 0.49mm2
  • 1.2V Vdd
  • 2 drivers with enables -- Can either drive a
    monopole or dipole
  • Each driver with 16 levels of driving capabilities

Driver
Write a Comment
User Comments (0)
About PowerShow.com