Lab Project 1 22x3 Memory Design Due 102507

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Lab Project 1 22x3 Memory Design (Due 10/25/07)

• The bus signals are Dlt02gt, Alt03gt, AE (address
  enable), R/W
• Clearly show the master, decoders, muxes, and
  bus.
• Data is transferred on the falling edge of the
  clock.
• Use LEDs to display bus signals.
• Use tristate buffers to drive the bus data lines
  (why?).
• Part 1
• Clearly explain your design
• Show the timing diagrams for the design
  implementation
• Part 2
• Implement your design on the LogicWorks5
  Simulator
• Capture the timing diagrams from the Simulator
  for your report
• Part 3 (with ONE partner)
• Build a circuit(s) in the Laboratory
• Capture the oscilloscope traces for your report
• Part 4