Title: ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Power Analysis: High-Level
1ELEC 5970-001/6970-001(Fall 2005)Special Topics
in Electrical EngineeringLow-Power Design of
Electronic CircuitsPower Analysis High-Level
- Vishwani D. Agrawal
- James J. Danaher Professor
- Department of Electrical and Computer Engineering
- Auburn University
- http//www.eng.auburn.edu/vagrawal
- vagrawal_at_eng.auburn.edu
2Key Parameters
Power a Capacitance Activity
- Capacitance
- Area
- Complexity
- Activity
- Dynamic behavior
- Operational characteristics
3Architecture-Level Power Estimation
- Analytical methods
- Complexity-based models
- Activity-based models
- Empirical methods
- Fixed-activity models
- Activity-sensitive models
4A Complexity-Based Model
Power S GEk (Etyp CLkVDD2) f Ak All
functional blocks k
- where
- GEk gate equivalent count for block k, e.g.,
estimated number of 2-input NANDs. - Etyp average energy consumed by an active
typical - 2-input NAND.
- CLk average capacitance of a gate in block k.
- f clock freqency.
- VDD supply voltage.
- Ak average fraction of gates switching in block
k.
Ref. K. Müller-Glaser, K. Kirsch and K.
Neusinger, Estimating Essential Design
Characteristics to Support Project Planning for
ASIC Design Management, Proc. IEEE Int. Conf.
CAD, Nov. 1991, pp. 148-151.
5Improving Complexity Models
- Treat logic, memory, interconnects and clock
tree, separately - For example, a memory array may not be modeled as
equivalent NAND gates, but as a memory cell.
6An On-Chip SRAM
2k cells
Memory array
word line
Six-transistor memory cell
. . .
. . .
Address bus
bit line
Row decode and drivers
2n-k cells
. . .
Sense and column decode
Ctrl
. . .
Data bus
7Power Consumed by SRAM
2k Power -- (cint lcol 2n-k
ctr) VDD Vswing f 2
Where 2k number of cells in a row cint wire
capacitance per unit length lcol memory column
length 2n-k number of cells in a
column ctr minimum size transistor drain
capacitance Vswing bitline voltage swing
Ref. D. Liu and C. Svenson, Power Consumption
Estimation in CMOS VLSI Chips, IEEE J.
Solid-State Circuits, June 1991, pp. 663-670.
8Activity-Based Models
- Power a capacitance activity
- Capacitance a area
- Both area and activity can be estimated from the
entropy of a Boolean function. - Definition Entropy of a system with m states
having probabilities p1, p2, . . . , pm, is - m
- H - S pk log2 pk bits
- k1
9Binary Signals
- Entropy of a binary signal
- H(p1) - p1 log2 p1 (1- p1) log2(1-p1)
- Entropy of an n-bit binary vector
- n
- H(X) S H(p1k)
- k1
10Entropy and Activity
1.0 0.75 0.50 0.25 0.0
4 p1k(1-p1k)
Entropy
0.0 0.25 0.5 0.75 1.0
p1k
11Entropy of a Circuit
Combinational Logic
Y1 Y2 Ym
X1 X2 Xn
. . .
. . .
12Input and Output Entropy
2n Hi S pk log2 pk k1 where pk
probability of kth input vector
2m Ho S pj log2 pj j1 where pj
probability of jth output vector
13Average Acrivity
2/3 Average entropy --- (Hi
2Ho) nm
Quadratic decay
Hi
Hi Ho
Ho
PI
PO
Circuit depth ?
14Area Estimate
- K.-T. Cheng and V. D. Agrawal, An Entropy
Measure for the Complexity of Multi-Output
Boolean Functions, Proc. 17th DAC, 1990, pp.
302-305. - M. Nemani and F. Najm, Towards a High-Level
Power Estimation Capability, IEEE Trans. CAD,
vol. 15, no. 6, pp. 588-598, June 1996.
Area 2n Ho/n for large n 2n Ho for n 10
15Power
N Power K1 Av. Activity S Ck
K2 Av. Activity Area k1 where Ck is
the capacitance of kth node in a circuit with N
nodes 2n1 Power K3 ------ Ho
(Hi Ho) 3n(nm) Constant K3 is
determined by simulation of gate-level circuits.
16Sequential Circuit
Combinational Logic
PI
PO
Ho
Hi
Flip-flops
Hi and Ho are determined from high-level
simulation.
17Empirical Methods
- Functional blocks are characterized for power
consumption in active and inactive (standby)
modes by - Analytical methods, or
- Simulation, or
- Measurement
- A software simulator determined which blocks
become active and adds their power consumption.
18Example RISC Microprocessor
Clock cycles 1 2 3 4 5 6 . . .
add R1?R2R3
IF ID EX MEM WB
mem rfile ALU rfile pcadd bradd
IF ID EX MEM WB
lw R4?4(R5)
mem rfile ALU mem rfile pcadd bradd
ALU
mem
ALU
Power profile
mem
mem
ALU
ALU
rfile
rfile
ALU
ALU
rfile
rfile
time
19Additional References
- P. E. Landman, A Survey of High-Level Power
Estimation Techniques, in Low-Power CMOS Design,
A. Chandrakasan and R. Brodersen (Editors), New
York IEEE Press, 1998. - P. E. Landman and J. M. Rabaey,
Activity-Sensitive Architectural Power
Analysis, IEEE Trans. CAD, vol. 15, no. 6, pp.
571-587, June 1996.