CS35101 Computer Architecture Spring 2006 Week 5

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CS35101Computer ArchitectureSpring 2006Week 5

• Paul Durand (www.cs.kent.edu/durand)
• Course url www.cs.kent.edu/durand/cs35101.htm

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Heads Up

• This weeks material
• MIPS procedures (contd), immediate instructions,
  and addressing modes
• Reading assignment - PH 3.6, A.6 and 3.8
• Translating a program
• Reading assignment PH 2.10 2.12 and A.1-A.5
• Reminders
• HW2 is due Monday, February 20th (by midnight)
• Midterm 1 Thursday, February 23rd
• Next weeks material

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Review MIPS Organization, so far
Processor

Memory
Register File
11100
src1 addr
src1 data
5
32
src2 addr
32 registers (zero - ra)
5
dst addr
read/write addr
src2 data
5
write data
230 words
32
32
32
32 bits
br offset
read data
32
Add
PC
32
32
32
32
Add
32
4
write data
01100
32
01000
32
00100
7
6
5
4
32
00000
ALU
0
1
2
3
32
word address (binary)
32 bits
32
byte address (big Endian)
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• Cray was a legend in computers said that he
  liked to hire inexperienced engineers right out
  of school, because they do not usually know
  whats supposed to be impossible.
• The Soul of a New Machine, Kidder, pg. 77

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Review MIPS ISA, so far
Category Instr Op Code Example Meaning
Arithmetic (R format) add 0 and 32 add s1, s2, s3 s1 s2 s3
Arithmetic (R format) subtract 0 and 34 sub s1, s2, s3 s1 s2 - s3
Data Transfer (I format) load word 35 lw s1, 100(s2) s1 Memory(s2100)
Data Transfer (I format) store word 43 sw s1, 100(s2) Memory(s2100) s1
Data Transfer (I format) load byte 32 lb s1, 101(s2) s1 Memory(s2101)
Data Transfer (I format) store byte 40 sb s1, 101(s2) Memory(s2101) s1
Cond. Branch (I R format) br on equal 4 beq s1, s2, L if (s1s2) go to L
Cond. Branch (I R format) br on not equal 5 bne s1, s2, L if (s1 !s2) go to L
Cond. Branch (I R format) set on less than 0 and 42 slt s1, s2, s3 if (s2lts3) s11 else s10
Uncond. Jump (J R format) jump 2 j 2500 go to 10000
Uncond. Jump (J R format) jump register 0 and 8 jr t1 go to t1
Uncond. Jump (J R format) jump and link 3 jal 2500 go to 10000 raPC4
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Review MIPS Organization, so far
Processor

Memory
Register File
11100
src1 addr
src1 data
5
32
src2 addr
32 registers (zero - ra)
5
dst addr
read/write addr
src2 data
5
write data
230 words
32
32
32
32 bits
br offset
read data
32
Add
PC
32
32
32
32
Add
32
4
write data
01100
32
01000
32
00100
7
6
5
4
32
00000
ALU
0
1
2
3
32
word address (binary)
32 bits
32
byte address (big Endian)
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Branching Far Away

• What if the branch destination is further away
  than can be captured in 16 bits?

• The assembler comes to the rescue it inserts an
  unconditional jump to the branch target and
  inverts the condition
• beq s0, s1, L1
• becomes
• bne s0, s1, L2
• j L1
• L2

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Dealing with Constants

• Small constants are used quite frequently (often
  50 of operands)
• e.g., A A 5 B B 1 C C - 18
• Solutions? Why not?
• put typical constants in memory and load them
• create hard-wired registers (like zero) for
  constants like 1

• Allow for MIPS instructions like addi sp,
  sp, 4 slti t0, t1, 10 andi t0, t0,
  6 ori t0, t0, 4
• How do we make this work?

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Immediate Operands

• MIPS immediate instructions addi sp, sp,
  4 sp sp 4
• slti t0, s2, 15 t0 1 if s2lt15
• Machine format
• The constant is kept inside the instruction
  itself!
• I format Immediate format
• Limits immediate values to the range 2151 to
  -215

I format
op rs rt 16
bit immediate
8 29 29
4
10 18 8
15
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How About Larger Constants?

• We'd also like to be able to load a 32 bit
  constant into a register
• Must use two instructions, new "load upper
  immediate" instruction lui t0, 1010101010101010
• Then must get the lower order bits right, i.e.,
  ori t0, t0, 1010101010101010

16 0 8
1010101010101010
1010101010101010
0000000000000000
0000000000000000
1010101010101010
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How About Larger Constants?

• We'd also like to be able to load a 32 bit
  constant into a register
• Must use two instructions, new "load upper
  immediate" instruction lui t0, 1010101010101010
• Then must get the lower order bits right, i.e.,
  ori t0, t0, 1010101010101010

16 0 8
1010101010101010
1010101010101010
0000000000000000
0000000000000000
1010101010101010
1010101010101010 1010101010101010
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MIPS Addressing Modes

• Register addressing operand is in a register
• Base (displacement) addressing operand is at
  the memory location whose address is the sum of a
  register and a 16-bit constant contained within
  the instruction
• Immediate addressing operand is a 16-bit
  constant contained within the instruction
• PC-relative addressing instruction address is
  the sum of the PC and a 16-bit constant contained
  within the instruction
• Pseudo-direct addressing instruction address is
  the 26-bit constant contained within the
  instruction concatenated with the upper 4 bits of
  the PC

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Addressing Modes Illustrated
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Design Principles

• Simplicity favors regularity
• fixed size instructions 32-bits
• small number of instruction formats
• Smaller is faster
• limited instruction set
• limited number of registers in register file
• limited number of addressing modes
• Good design demands good compromises
• three instruction formats
• Make the common case fast
• arithmetic operands from the register file
  (load-store machine)
• allow instructions to contain immediate operands

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Review MIPS ISA, so far
Category Instr Op Code Example Meaning
Arithmetic (R I format) add 0 and 32 add s1, s2, s3 s1 s2 s3
Arithmetic (R I format) subtract 0 and 34 sub s1, s2, s3 s1 s2 - s3
Arithmetic (R I format) add immediate 8 addi s1, s2, 6 s1 s2 6
Arithmetic (R I format) or immediate 13 ori s1, s2, 6 s1 s2 v 6
Data Transfer (I format) load word 35 lw s1, 24(s2) s1 Memory(s224)
Data Transfer (I format) store word 43 sw s1, 24(s2) Memory(s224) s1
Data Transfer (I format) load byte 32 lb s1, 25(s2) s1 Memory(s225)
Data Transfer (I format) store byte 40 sb s1, 25(s2) Memory(s225) s1
Data Transfer (I format) load upper imm 15 lui s1, 6 s1 6 216
Cond. Branch (I R format) br on equal 4 beq s1, s2, L if (s1s2) go to L
Cond. Branch (I R format) br on not equal 5 bne s1, s2, L if (s1 !s2) go to L
Cond. Branch (I R format) set on less than 0 and 42 slt s1, s2, s3 if (s2lts3) s11 else s10
Cond. Branch (I R format) set on less than immediate 10 slti s1, s2, 6 if (s2lt6) s11 else s10
Uncond. Jump (J R format) jump 2 j 2500 go to 10000
Uncond. Jump (J R format) jump register 0 and 8 jr t1 go to t1
Uncond. Jump (J R format) jump and link 3 jal 2500 go to 10000 raPC4
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The Code Translation Hierarchy
C program
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Compiler

• Transforms the C program into an assembly
  language program
• Advantages of high-level languages
• many fewer lines of code
• easier to understand and debug
• Todays optimizing compilers can produce assembly
  code nearly as good as an assembly language
  programming expert and often better for large
  programs
• good smaller code size, faster execution
• and even lower power consuming!

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Assembler

• Transforms symbolic assembler code into object
  (machine) code
• Advantages of assembler
• much easier than remembering instruction binary
  codes
• can use labels for addresses and let the
  assembler do the arithmetic
• can use pseudo-instructions
• e.g., move t0, t1 exists only in assembler
  (would be implemented using add t0,t1,zero)
• However, must remember that machine language is
  the underlying reality
• e.g., destination is no longer specified first
• And, when considering performance, you should
  count real instructions executed, not code size

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Other Tasks of the Assembler

• Determines binary addresses corresponding to all
  labels
• keeps track of labels used in branches and data
  transfer instructions in a symbol table
• pairs of symbols and addresses
• Converts pseudo-instructions to legal assembly
  code
• register at is reserved for the assembler to do
  this
• Converts branches to far away locations into a
  branch followed by a jump
• Converts instructions with large immediates into
  a load upper immediate followed by an or
  immediate
• Converts numbers specified in decimal and
  hexidecimal into their binary equivalents
• Converts characters into their ASCII equivalents

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Typical Object File Pieces

• Object file header size and position of
  following pieces
• Text module assembled object (machine) code
• Data module data accompanying the code
• static data - allocated throughout the program
• dynamic data - grows and shrinks as needed by the
  program
• Relocation information identifies instructions
  (data) that use (are located at) absolute
  addresses those that are not relative to a
  register (e.g., jump destination addr) when the
  code and data is loaded into memory
• Symbol table remaining undefined labels (e.g.,
  external references)
• Debugging information

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MIPS (spim) Memory Allocation
Memory
f f f f f f f c
Mem Map I/O
Kernel Code Data
8000 0080
sp
7f f e f f fc
Stack
230 words
Dynamic data
gp
1000 8000 (? 1004 0000)
Static data
1000 0000
Your Code
0040 0000
PC
Reserved
0000 0000
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Linker

• Takes all of the independently assembled code
  segments and stitches (links) them together
• Much faster to patch code and recompile and
  reassemble that patched routine, than it is to
  recompile and reassemble the entire program
• Decides on memory allocation pattern for the code
  and data modules of each segment
• remember, segments were assembled in isolation so
  each assumes its codes starting location is
  0x0040 0000 and its static data starting location
  is 0x1000 0000
• Absolute addresses must be relocated to reflect
  the new starting location of each code and data
  module
• Uses the symbol table information to resolve all
  remaining undefined labels
• branches, jumps, and data addresses to external
  segments

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Loader

• Loads (copies) the executable code now stored on
  disk into memory at the starting address
  specified by the operating system
• Initializes the machine registers and sets the
  stack pointer to the first free location (0x7ffe
  fffc)
• Copies the parameters (if any) to the main
  routine onto the stack
• Jumps to a start-up routine (at PC addr 0x0040
  0000 on xspim) that copies the parameters into
  the argument registers and then calls the main
  routine of the program with a jal main